Module Name: src Committed By: riastradh Date: Thu Sep 22 14:42:10 UTC 2022
Modified Files: src/sys/arch/x86/pci: ichlpcib.c tco.c src/sys/dev/ic: i82801lpcreg.h Log Message: ichlpcib(4), tco(4): Take `lpcib_' off various names. For PMC-specific ones, change `lpcib_' to `pmc_'. These are in a separate PCI device in newer chipsets. For TCO-specific ones, which may live in different places, whether at their own base address or as an offset from PMBASE, just leave it as `tco_' or `tcotimer'. No functional change intended. To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/x86/pci/ichlpcib.c cvs rdiff -u -r1.5 -r1.6 src/sys/arch/x86/pci/tco.c cvs rdiff -u -r1.12 -r1.13 src/sys/dev/ic/i82801lpcreg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/x86/pci/ichlpcib.c diff -u src/sys/arch/x86/pci/ichlpcib.c:1.56 src/sys/arch/x86/pci/ichlpcib.c:1.57 --- src/sys/arch/x86/pci/ichlpcib.c:1.56 Thu Sep 22 14:41:49 2022 +++ src/sys/arch/x86/pci/ichlpcib.c Thu Sep 22 14:42:09 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: ichlpcib.c,v 1.56 2022/09/22 14:41:49 riastradh Exp $ */ +/* $NetBSD: ichlpcib.c,v 1.57 2022/09/22 14:42:09 riastradh Exp $ */ /*- * Copyright (c) 2004 The NetBSD Foundation, Inc. @@ -40,7 +40,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.56 2022/09/22 14:41:49 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: ichlpcib.c,v 1.57 2022/09/22 14:42:09 riastradh Exp $"); #include <sys/types.h> #include <sys/param.h> @@ -607,7 +607,7 @@ pmtimer_configure(device_t self) /* Attach our PM timer with the generic acpipmtimer function */ sc->sc_pmtimer = acpipmtimer_attach(self, sc->sc_iot, sc->sc_ioh, - LPCIB_PM1_TMR, 0); + PMC_PM1_TMR, 0); } static int @@ -765,9 +765,9 @@ speedstep_sysctl_helper(SYSCTLFN_ARGS) * sysctl_lookup() which can both copyin and copyout. */ s = splserial(); - state = SS_READ(sc, LPCIB_PM_SS_CNTL); + state = SS_READ(sc, PMC_PM_SS_CNTL); splx(s); - if ((state & LPCIB_PM_SS_STATE_LOW) == 0) + if ((state & PMC_PM_SS_STATE_LOW) == 0) ostate = 1; else ostate = 0; @@ -787,8 +787,8 @@ speedstep_sysctl_helper(SYSCTLFN_ARGS) } s = splserial(); - state2 = SS_READ(sc, LPCIB_PM_SS_CNTL); - if ((state2 & LPCIB_PM_SS_STATE_LOW) == 0) + state2 = SS_READ(sc, PMC_PM_SS_CNTL); + if ((state2 & PMC_PM_SS_STATE_LOW) == 0) ostate = 1; else ostate = 0; @@ -797,17 +797,17 @@ speedstep_sysctl_helper(SYSCTLFN_ARGS) uint8_t cntl; if (nstate == 0) - state2 |= LPCIB_PM_SS_STATE_LOW; + state2 |= PMC_PM_SS_STATE_LOW; else - state2 &= ~LPCIB_PM_SS_STATE_LOW; + state2 &= ~PMC_PM_SS_STATE_LOW; /* * Must disable bus master arbitration during the change. */ - cntl = SS_READ(sc, LPCIB_PM_CTRL); - SS_WRITE(sc, LPCIB_PM_CTRL, cntl | LPCIB_PM_SS_CNTL_ARB_DIS); - SS_WRITE(sc, LPCIB_PM_SS_CNTL, state2); - SS_WRITE(sc, LPCIB_PM_CTRL, cntl); + cntl = SS_READ(sc, PMC_PM_CTRL); + SS_WRITE(sc, PMC_PM_CTRL, cntl | PMC_PM_SS_CNTL_ARB_DIS); + SS_WRITE(sc, PMC_PM_SS_CNTL, state2); + SS_WRITE(sc, PMC_PM_CTRL, cntl); } splx(s); out: Index: src/sys/arch/x86/pci/tco.c diff -u src/sys/arch/x86/pci/tco.c:1.5 src/sys/arch/x86/pci/tco.c:1.6 --- src/sys/arch/x86/pci/tco.c:1.5 Thu Sep 22 14:41:49 2022 +++ src/sys/arch/x86/pci/tco.c Thu Sep 22 14:42:09 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: tco.c,v 1.5 2022/09/22 14:41:49 riastradh Exp $ */ +/* $NetBSD: tco.c,v 1.6 2022/09/22 14:42:09 riastradh Exp $ */ /*- * Copyright (c) 2015 The NetBSD Foundation, Inc. @@ -34,7 +34,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: tco.c,v 1.5 2022/09/22 14:41:49 riastradh Exp $"); +__KERNEL_RCSID(0, "$NetBSD: tco.c,v 1.6 2022/09/22 14:42:09 riastradh Exp $"); #include <sys/types.h> #include <sys/param.h> @@ -129,18 +129,18 @@ tco_attach(device_t parent, device_t sel * Enable TCO timeout SMI only if the hardware reset does not * work. We don't know what the SMBIOS does. */ - ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN); - ioreg &= ~LPCIB_SMI_EN_TCO_EN; + ioreg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, PMC_SMI_EN); + ioreg &= ~PMC_SMI_EN_TCO_EN; /* * Clear the No Reboot (NR) bit. If this fails, enabling the TCO_EN bit * in the SMI_EN register is the last chance. */ if (tcotimer_disable_noreboot(self)) { - ioreg |= LPCIB_SMI_EN_TCO_EN; + ioreg |= PMC_SMI_EN_TCO_EN; } - if ((ioreg & LPCIB_SMI_EN_GBL_SMI_EN) != 0) { - bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPCIB_SMI_EN, ioreg); + if ((ioreg & PMC_SMI_EN_GBL_SMI_EN) != 0) { + bus_space_write_4(sc->sc_iot, sc->sc_ioh, PMC_SMI_EN, ioreg); } /* Reset the watchdog status registers. */ @@ -163,19 +163,19 @@ tco_attach(device_t parent, device_t sel */ switch (sc->sc_version) { case TCO_VERSION_RCBA: - sc->sc_max_t = LPCIB_TCOTIMER2_MAX_TICK; - sc->sc_min_t = LPCIB_TCOTIMER2_MIN_TICK; + sc->sc_max_t = TCOTIMER2_MAX_TICK; + sc->sc_min_t = TCOTIMER2_MIN_TICK; break; case TCO_VERSION_PCIB: - sc->sc_max_t = LPCIB_TCOTIMER_MAX_TICK; - sc->sc_min_t = LPCIB_TCOTIMER_MIN_TICK; + sc->sc_max_t = TCOTIMER_MAX_TICK; + sc->sc_min_t = TCOTIMER_MIN_TICK; break; } - sc->sc_smw.smw_period = lpcib_tcotimer_tick_to_second(sc->sc_max_t); + sc->sc_smw.smw_period = tcotimer_tick_to_second(sc->sc_max_t); aprint_verbose_dev(self, "Min/Max interval %u/%u seconds\n", - lpcib_tcotimer_tick_to_second(sc->sc_min_t), - lpcib_tcotimer_tick_to_second(sc->sc_max_t)); + tcotimer_tick_to_second(sc->sc_min_t), + tcotimer_tick_to_second(sc->sc_max_t)); if (sysmon_wdog_register(&sc->sc_smw)) aprint_error_dev(self, "unable to register TCO timer" @@ -232,7 +232,7 @@ tcotimer_setmode(struct sysmon_wdog *smw /* Stop the TCO timer. */ tcotimer_stop(sc); } else { - period = lpcib_tcotimer_second_to_tick(smw->smw_period); + period = tcotimer_second_to_tick(smw->smw_period); if (period < sc->sc_min_t || period > sc->sc_max_t) return EINVAL; @@ -244,18 +244,18 @@ tcotimer_setmode(struct sysmon_wdog *smw case TCO_VERSION_RCBA: /* ICH6 or newer */ ich6period = bus_space_read_2(sc->sc_iot, sc->sc_ioh, - LPCIB_TCO_TMR2); + PMC_TCO_TMR2); ich6period &= 0xfc00; bus_space_write_2(sc->sc_iot, sc->sc_ioh, - LPCIB_TCO_TMR2, ich6period | period); + PMC_TCO_TMR2, ich6period | period); break; case TCO_VERSION_PCIB: /* ICH5 or older */ ich5period = bus_space_read_1(sc->sc_iot, sc->sc_ioh, - LPCIB_TCO_TMR); + PMC_TCO_TMR); ich5period &= 0xc0; bus_space_write_1(sc->sc_iot, sc->sc_ioh, - LPCIB_TCO_TMR, ich5period | period); + PMC_TCO_TMR, ich5period | period); break; } @@ -275,10 +275,10 @@ tcotimer_tickle(struct sysmon_wdog *smw) /* any value is allowed */ switch (sc->sc_version) { case TCO_VERSION_RCBA: - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO_RLD, 1); break; case TCO_VERSION_PCIB: - bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_TCO_RLD, 1); + bus_space_write_1(sc->sc_iot, sc->sc_ioh, PMC_TCO_RLD, 1); break; } @@ -290,9 +290,9 @@ tcotimer_stop(struct tco_softc *sc) { uint16_t ioreg; - ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); - ioreg |= LPCIB_TCO1_CNT_TCO_TMR_HLT; - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); + ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, PMC_TCO1_CNT); + ioreg |= PMC_TCO1_CNT_TCO_TMR_HLT; + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO1_CNT, ioreg); } static void @@ -300,20 +300,20 @@ tcotimer_start(struct tco_softc *sc) { uint16_t ioreg; - ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT); - ioreg &= ~LPCIB_TCO1_CNT_TCO_TMR_HLT; - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_CNT, ioreg); + ioreg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, PMC_TCO1_CNT); + ioreg &= ~PMC_TCO1_CNT_TCO_TMR_HLT; + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO1_CNT, ioreg); } static void tcotimer_status_reset(struct tco_softc *sc) { - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO1_STS, - LPCIB_TCO1_STS_TIMEOUT); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, - LPCIB_TCO2_STS_BOOT_STS); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, LPCIB_TCO2_STS, - LPCIB_TCO2_STS_SECONDS_TO_STS); + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO1_STS, + PMC_TCO1_STS_TIMEOUT); + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO2_STS, + PMC_TCO2_STS_BOOT_STS); + bus_space_write_2(sc->sc_iot, sc->sc_ioh, PMC_TCO2_STS, + PMC_TCO2_STS_SECONDS_TO_STS); } /* Index: src/sys/dev/ic/i82801lpcreg.h diff -u src/sys/dev/ic/i82801lpcreg.h:1.12 src/sys/dev/ic/i82801lpcreg.h:1.13 --- src/sys/dev/ic/i82801lpcreg.h:1.12 Fri Dec 26 05:09:03 2014 +++ src/sys/dev/ic/i82801lpcreg.h Thu Sep 22 14:42:09 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: i82801lpcreg.h,v 1.12 2014/12/26 05:09:03 msaitoh Exp $ */ +/* $NetBSD: i82801lpcreg.h,v 1.13 2022/09/22 14:42:09 riastradh Exp $ */ /*- * Copyright (c) 2004 The NetBSD Foundation, Inc. @@ -111,40 +111,40 @@ * Power management I/O registers * (offset from PMBASE) */ -#define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */ -#define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */ -#define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */ -#define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */ -#define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */ -#define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */ -#define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */ -# define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */ -#define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */ -#define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */ -#define LPCIB_SMI_EN 0x30 -# define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18) -# define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17) -# define LPCIB_SMI_EN_PERIODIC_EN (1 << 14) -# define LPCIB_SMI_EN_TCO_EN (1 << 13) -# define LPCIB_SMI_EN_MCSMI_EN (1 << 11) -# define LPCIB_SMI_EN_BIOS_RLS (1 << 7) -# define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6) -# define LPCIB_SMI_EN_APMC_EN (1 << 5) -# define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4) -# define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3) -# define LPCIB_SMI_EN_BIOS_EN (1 << 2) -# define LPCIB_SMI_EN_EOS (1 << 1) -# define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0) -#define LPCIB_SMI_STS 0x34 -#define LPCIB_ALT_GP_SMI_EN 0x38 -#define LPCIB_ALT_GP_SMI_STS 0x3a -#define LPCIB_MON_SMI 0x40 -#define LPCIB_DEVACT_STS 0x44 -#define LPCIB_DEVTRAP_EN 0x48 -#define LPCIB_BUS_ADDR_TRACK 0x4c -#define LPCIB_BUS_CYC_TRACK 0x4e -#define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */ -# define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */ +#define PMC_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */ +#define PMC_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */ +#define PMC_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */ +#define PMC_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */ +#define PMC_PROC_CNT 0x10 /* ACPI P_BLK processor control */ +#define PMC_LV2 0x14 /* ACPI P_BLK processor C2 control */ +#define PMC_PM_CTRL 0x20 /* ACPI Power Management Control */ +# define PMC_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */ +#define PMC_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */ +#define PMC_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */ +#define PMC_SMI_EN 0x30 +# define PMC_SMI_EN_INTEL_USB2_EN (1 << 18) +# define PMC_SMI_EN_LEGACY_USB2_EN (1 << 17) +# define PMC_SMI_EN_PERIODIC_EN (1 << 14) +# define PMC_SMI_EN_TCO_EN (1 << 13) +# define PMC_SMI_EN_MCSMI_EN (1 << 11) +# define PMC_SMI_EN_BIOS_RLS (1 << 7) +# define PMC_SMI_EN_SWSMI_TMR_EN (1 << 6) +# define PMC_SMI_EN_APMC_EN (1 << 5) +# define PMC_SMI_EN_SLP_SMI_EN (1 << 4) +# define PMC_SMI_EN_LEGACY_USB_EN (1 << 3) +# define PMC_SMI_EN_BIOS_EN (1 << 2) +# define PMC_SMI_EN_EOS (1 << 1) +# define PMC_SMI_EN_GBL_SMI_EN (1 << 0) +#define PMC_SMI_STS 0x34 +#define PMC_ALT_GP_SMI_EN 0x38 +#define PMC_ALT_GP_SMI_STS 0x3a +#define PMC_MON_SMI 0x40 +#define PMC_DEVACT_STS 0x44 +#define PMC_DEVTRAP_EN 0x48 +#define PMC_BUS_ADDR_TRACK 0x4c +#define PMC_BUS_CYC_TRACK 0x4e +#define PMC_PM_SS_CNTL 0x50 /* SpeedStep control */ +# define PMC_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */ /* * General Purpose I/O Registers @@ -255,29 +255,29 @@ * System management TCO registers * (offset from PMBASE) */ -#define LPCIB_TCO_BASE 0x60 -#define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00) -#define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01) -#define LPCIB_TCO_TMR2 (LPCIB_TCO_BASE+0x12) /* ICH6 and newer */ -# define LPCIB_TCO_TMR_MASK 0x3f -#define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02) -#define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03) -#define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04) -# define LPCIB_TCO1_STS_TIMEOUT 0x08 -#define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06) -# define LPCIB_TCO2_STS_BOOT_STS 0x04 -# define LPCIB_TCO2_STS_SECONDS_TO_STS 0x02 -#define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08) -# define LPCIB_TCO1_CNT_TCO_LOCK (1 << 12) -# define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11) -# define LPCIB_TCO1_CNT_SEND_NOW (1 << 10) -# define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9) -# define LPCIB_TCO1_CNT_NMI_NOW (1 << 8) -#define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a) -#define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c) -#define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d) -#define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e) -#define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10) +#define PMC_TCO_BASE 0x60 +#define PMC_TCO_RLD (PMC_TCO_BASE+0x00) +#define PMC_TCO_TMR (PMC_TCO_BASE+0x01) +#define PMC_TCO_TMR2 (PMC_TCO_BASE+0x12) /* ICH6 and newer */ +# define PMC_TCO_TMR_MASK 0x3f +#define PMC_TCO_DAT_IN (PMC_TCO_BASE+0x02) +#define PMC_TCO_DAT_OUT (PMC_TCO_BASE+0x03) +#define PMC_TCO1_STS (PMC_TCO_BASE+0x04) +# define PMC_TCO1_STS_TIMEOUT 0x08 +#define PMC_TCO2_STS (PMC_TCO_BASE+0x06) +# define PMC_TCO2_STS_BOOT_STS 0x04 +# define PMC_TCO2_STS_SECONDS_TO_STS 0x02 +#define PMC_TCO1_CNT (PMC_TCO_BASE+0x08) +# define PMC_TCO1_CNT_TCO_LOCK (1 << 12) +# define PMC_TCO1_CNT_TCO_TMR_HLT (1 << 11) +# define PMC_TCO1_CNT_SEND_NOW (1 << 10) +# define PMC_TCO1_CNT_NMI2SMI_EN (1 << 9) +# define PMC_TCO1_CNT_NMI_NOW (1 << 8) +#define PMC_TCO2_CNT (PMC_TCO_BASE+0x0a) +#define PMC_TCO_MESSAGE1 (PMC_TCO_BASE+0x0c) +#define PMC_TCO_MESSAGE2 (PMC_TCO_BASE+0x0d) +#define PMC_TCO_WDSTATUS (PMC_TCO_BASE+0x0e) +#define PMC_SW_IRQ_GEN (PMC_TCO_BASE+0x10) /* * TCO timer tick. ICH datasheets say: @@ -285,20 +285,20 @@ * - 6 bit; values of 0-3 will be ignored and should not be attempted */ static __inline int -lpcib_tcotimer_tick_to_second(int ltick) +tcotimer_tick_to_second(int ltick) { return ltick * 6 / 10; } static __inline int -lpcib_tcotimer_second_to_tick(int ltick) +tcotimer_second_to_tick(int ltick) { return ltick * 10 / 6; } -#define LPCIB_TCOTIMER_MIN_TICK 4 -#define LPCIB_TCOTIMER2_MIN_TICK 2 -#define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ -#define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ +#define TCOTIMER_MIN_TICK 4 +#define TCOTIMER2_MIN_TICK 2 +#define TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ +#define TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ #endif /* _DEV_IC_I82801LPCREG_H_ */