Module Name: src
Committed By: msaitoh
Date: Wed Sep 28 10:09:48 UTC 2022
Modified Files:
src/sys/arch/x86/pci/imcsmb: imc.c
Log Message:
Fix compile error.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/x86/pci/imcsmb/imc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/imcsmb/imc.c
diff -u src/sys/arch/x86/pci/imcsmb/imc.c:1.4 src/sys/arch/x86/pci/imcsmb/imc.c:1.5
--- src/sys/arch/x86/pci/imcsmb/imc.c:1.4 Sat Aug 7 16:19:08 2021
+++ src/sys/arch/x86/pci/imcsmb/imc.c Wed Sep 28 10:09:48 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: imc.c,v 1.4 2021/08/07 16:19:08 thorpej Exp $ */
+/* $NetBSD: imc.c,v 1.5 2022/09/28 10:09:48 msaitoh Exp $ */
/*-
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.4 2021/08/07 16:19:08 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.5 2022/09/28 10:09:48 msaitoh Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -137,12 +137,12 @@ __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.4
#define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8
#define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8
-#define IMCSMB_PCI_DEV_ID_IMC0_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC0_MAIN
+#define IMCSMB_PCI_DEV_ID_IMC0_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR
#define IMCSMB_PCI_DEV_ID_IMC0_BDX PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1
/* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
-#define IMCSMB_PCI_DEV_ID_IMC1_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC1_MAIN
+#define IMCSMB_PCI_DEV_ID_IMC1_HSX PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR
#define IMCSMB_PCI_DEV_ID_IMC1_BDX PCI_PRODUCT_INTEL_COREI76K_IMC_0
/* There are two SMBus controllers in each device. These define the registers
@@ -291,8 +291,8 @@ imc_probe(device_t dev, cfdata_t cf, voi
switch(PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_INTEL_COREI76K_IMC_0:
case PCI_PRODUCT_INTEL_XEOND_MEM_0_TTR_1:
- case PCI_PRODUCT_INTEL_XE5_V3_IMC0_MAIN:
- case PCI_PRODUCT_INTEL_XE5_V3_IMC1_MAIN:
+ case PCI_PRODUCT_INTEL_XE5_V3_IMC0_TATRR:
+ case PCI_PRODUCT_INTEL_XE5_V3_IMC1_TATRR:
case PCI_PRODUCT_INTEL_E5_IMC_TA:
case PCI_PRODUCT_INTEL_E5V2_IMC_TA:
return 1;
