Module Name: src
Committed By: rin
Date: Wed Oct 5 08:18:00 UTC 2022
Modified Files:
src/sys/arch/powerpc/ibm4xx: clock.c copyinstr.c copyoutstr.c cpu.c
ibm4xx_machdep.c pmap.c trap.c
Log Message:
Minor style fixes to asm codes. No binary changes.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/powerpc/ibm4xx/clock.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/powerpc/ibm4xx/copyinstr.c \
src/sys/arch/powerpc/ibm4xx/copyoutstr.c
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/powerpc/ibm4xx/cpu.c
cvs rdiff -u -r1.37 -r1.38 src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/powerpc/ibm4xx/pmap.c
cvs rdiff -u -r1.100 -r1.101 src/sys/arch/powerpc/ibm4xx/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/powerpc/ibm4xx/clock.c
diff -u src/sys/arch/powerpc/ibm4xx/clock.c:1.32 src/sys/arch/powerpc/ibm4xx/clock.c:1.33
--- src/sys/arch/powerpc/ibm4xx/clock.c:1.32 Fri Mar 5 06:06:34 2021
+++ src/sys/arch/powerpc/ibm4xx/clock.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.32 2021/03/05 06:06:34 rin Exp $ */
+/* $NetBSD: clock.c,v 1.33 2022/10/05 08:18:00 rin Exp $ */
/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
/*
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.32 2021/03/05 06:06:34 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.33 2022/10/05 08:18:00 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ppcarch.h"
@@ -218,9 +218,9 @@ get_ppc4xx_timecount(struct timecounter
u_long tb;
int msr;
- __asm volatile ("mfmsr %0; wrteei 0" : "=r"(msr) :);
+ __asm volatile ("mfmsr %0; wrteei 0" : "=r" (msr));
tb = mftbl();
- __asm volatile ("mtmsr %0" :: "r"(msr));
+ __asm volatile ("mtmsr %0" :: "r" (msr));
return tb;
}
@@ -240,23 +240,26 @@ delay(unsigned int n)
tbh = tb >> 32;
tbl = tb;
__asm volatile (
+ "1:"
#ifdef PPC_IBM403
- "1: mftbhi %0 \n"
+ "mftbhi %0;"
#else
- "1: mftbu %0 \n"
+ "mftbu %0;"
#endif
- " cmplw %0,%1 \n"
- " blt 1b \n"
- " bgt 2f \n"
+ "cmplw %0,%1;"
+ "blt 1b;"
+ "bgt 2f;"
#ifdef PPC_IBM403
- " mftblo %0 \n"
+ "mftblo %0;"
#else
- " mftb %0 \n"
+ "mftb %0;"
#endif
- " cmplw %0,%2 \n"
- " blt 1b \n"
- "2: \n"
- : "=&r"(scratch) : "r"(tbh), "r"(tbl) : "cr0");
+ "cmplw %0,%2;"
+ "blt 1b;"
+ "2:"
+ : "=&r" (scratch)
+ : "r" (tbh), "r" (tbl)
+ : "cr0");
}
/*
Index: src/sys/arch/powerpc/ibm4xx/copyinstr.c
diff -u src/sys/arch/powerpc/ibm4xx/copyinstr.c:1.23 src/sys/arch/powerpc/ibm4xx/copyinstr.c:1.24
--- src/sys/arch/powerpc/ibm4xx/copyinstr.c:1.23 Wed Oct 5 02:56:14 2022
+++ src/sys/arch/powerpc/ibm4xx/copyinstr.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: copyinstr.c,v 1.23 2022/10/05 02:56:14 rin Exp $ */
+/* $NetBSD: copyinstr.c,v 1.24 2022/10/05 08:18:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: copyinstr.c,v 1.23 2022/10/05 02:56:14 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: copyinstr.c,v 1.24 2022/10/05 08:18:00 rin Exp $");
#include <sys/param.h>
#include <uvm/uvm_extern.h>
@@ -71,7 +71,7 @@ copyinstr(const void *uaddr, void *kaddr
}
resid = len;
- __asm volatile(
+ __asm volatile (
"mtctr %[resid];" /* Set up counter */
"mfmsr %[msr];" /* Save MSR */
"li %[tmp],0x20;" /* Disable IMMU */
Index: src/sys/arch/powerpc/ibm4xx/copyoutstr.c
diff -u src/sys/arch/powerpc/ibm4xx/copyoutstr.c:1.23 src/sys/arch/powerpc/ibm4xx/copyoutstr.c:1.24
--- src/sys/arch/powerpc/ibm4xx/copyoutstr.c:1.23 Wed Oct 5 02:56:14 2022
+++ src/sys/arch/powerpc/ibm4xx/copyoutstr.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: copyoutstr.c,v 1.23 2022/10/05 02:56:14 rin Exp $ */
+/* $NetBSD: copyoutstr.c,v 1.24 2022/10/05 08:18:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: copyoutstr.c,v 1.23 2022/10/05 02:56:14 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: copyoutstr.c,v 1.24 2022/10/05 08:18:00 rin Exp $");
#include <sys/param.h>
#include <uvm/uvm_extern.h>
@@ -71,7 +71,7 @@ copyoutstr(const void *kaddr, void *uadd
}
resid = len;
- __asm volatile(
+ __asm volatile (
"mtctr %[resid];" /* Set up counter */
"mfmsr %[msr];" /* Save MSR */
"li %[tmp],0x20;" /* Disable IMMU */
Index: src/sys/arch/powerpc/ibm4xx/cpu.c
diff -u src/sys/arch/powerpc/ibm4xx/cpu.c:1.38 src/sys/arch/powerpc/ibm4xx/cpu.c:1.39
--- src/sys/arch/powerpc/ibm4xx/cpu.c:1.38 Tue Mar 30 13:41:46 2021
+++ src/sys/arch/powerpc/ibm4xx/cpu.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.38 2021/03/30 13:41:46 simonb Exp $ */
+/* $NetBSD: cpu.c,v 1.39 2022/10/05 08:18:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.38 2021/03/30 13:41:46 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.39 2022/10/05 08:18:00 rin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -345,8 +345,8 @@ dcache_wbinv_page(vaddr_t va)
if (dcache_line_size) {
for (size_t i = 0; i < PAGE_SIZE; i += dcache_line_size) {
- __asm volatile("dcbf %0,%1" : : "b" (va), "r" (i));
+ __asm volatile ("dcbf %0,%1" : : "b" (va), "r" (i));
}
- __asm volatile("sync; isync" : : );
+ __asm volatile ("sync; isync");
}
}
Index: src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c
diff -u src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c:1.37 src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c:1.38
--- src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c:1.37 Tue Mar 30 14:33:10 2021
+++ src/sys/arch/powerpc/ibm4xx/ibm4xx_machdep.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: ibm4xx_machdep.c,v 1.37 2021/03/30 14:33:10 rin Exp $ */
+/* $NetBSD: ibm4xx_machdep.c,v 1.38 2022/10/05 08:18:00 rin Exp $ */
/* Original: ibm40x_machdep.c,v 1.3 2005/01/17 17:19:36 shige Exp $ */
/*
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ibm4xx_machdep.c,v 1.37 2021/03/30 14:33:10 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ibm4xx_machdep.c,v 1.38 2022/10/05 08:18:00 rin Exp $");
#include "ksyms.h"
@@ -295,7 +295,7 @@ ibm4xx_init(vaddr_t startkernel, vaddr_t
* Now enable translation (and machine checks/recoverable interrupts).
*/
__asm volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0; isync"
- : : "r"(0), "K"(PSL_IR|PSL_DR));
+ : : "r" (0), "K" (PSL_IR|PSL_DR));
/* XXXX PSL_ME - With ME set kernel gets stuck... */
/*
@@ -334,12 +334,12 @@ ibm4xx_install_extint(void (*handler)(vo
if (offset > 0x1ffffff)
panic("install_extint: too far away");
#endif
- __asm volatile ("mfmsr %0; wrteei 0" : "=r"(msr));
+ __asm volatile ("mfmsr %0; wrteei 0" : "=r" (msr));
extint_call = (extint_call & 0xfc000003) | offset;
memcpy((void *)EXC_EXI, &extint, (size_t)&extsize);
__syncicache((void *)&extint_call, sizeof extint_call);
__syncicache((void *)EXC_EXI, (int)&extsize);
- __asm volatile ("mtmsr %0" :: "r"(msr));
+ __asm volatile ("mtmsr %0" :: "r" (msr));
}
/*
Index: src/sys/arch/powerpc/ibm4xx/pmap.c
diff -u src/sys/arch/powerpc/ibm4xx/pmap.c:1.106 src/sys/arch/powerpc/ibm4xx/pmap.c:1.107
--- src/sys/arch/powerpc/ibm4xx/pmap.c:1.106 Mon Sep 12 08:02:44 2022
+++ src/sys/arch/powerpc/ibm4xx/pmap.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.106 2022/09/12 08:02:44 rin Exp $ */
+/* $NetBSD: pmap.c,v 1.107 2022/10/05 08:18:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.106 2022/09/12 08:02:44 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.107 2022/10/05 08:18:00 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ddb.h"
@@ -683,7 +683,7 @@ pmap_zero_page(paddr_t pa)
#else
for (i = PAGE_SIZE/CACHELINESIZE; i > 0; i--) {
- __asm volatile ("dcbz 0,%0" : : "r"(pa));
+ __asm volatile ("dcbz 0,%0" : : "r" (pa));
pa += CACHELINESIZE;
}
#endif
@@ -1197,8 +1197,8 @@ pmap_procwr(struct proc *p, vaddr_t va,
MTPID(%1)
"mtmsr %0;"
"isync;"
- : "=&r"(msr), "=&r"(opid)
- : "r"(ctx), "r"(va), "r"(len), "r"(CACHELINESIZE));
+ : "=&r" (msr), "=&r" (opid)
+ : "r" (ctx), "r" (va), "r" (len), "r" (CACHELINESIZE));
} else {
paddr_t pa;
vaddr_t tva, eva;
@@ -1246,16 +1246,16 @@ tlb_invalidate_entry(int i)
MTPID(%1)
"mtmsr %0;"
"isync;"
- : "=&r"(msr), "=&r"(pid), "=&r"(hi)
- : "r"(i), "r"(TLB_VALID));
+ : "=&r" (msr), "=&r" (pid), "=&r" (hi)
+ : "r" (i), "r" (TLB_VALID));
#else
/*
* Just clear entire TLBHI register.
*/
__asm volatile (
- "tlbwe %0,%1,0;"
+ "tlbwe %0,%1,0;"
"isync;"
- : : "r"(0), "r"(i));
+ : : "r" (0), "r" (i));
#endif
tlb_info[i].ti_ctx = 0;
@@ -1289,8 +1289,8 @@ ppc4xx_tlb_flush(vaddr_t va, int pid)
"beq 1f;"
"li %1,0;"
"1:"
- : "=&r"(i), "=&r"(found), "=&r"(msr)
- : "r"(va), "r"(pid));
+ : "=&r" (i), "=&r" (found), "=&r" (msr)
+ : "r" (va), "r" (pid));
if (found && !TLB_LOCKED(i)) {
/* Now flush translation */
@@ -1382,8 +1382,8 @@ ppc4xx_tlb_enter(int ctx, vaddr_t va, u_
MTPID(%1) /* Restore PID */
"mtmsr %0;" /* and MSR */
"isync;"
- : "=&r"(msr), "=&r"(pid)
- : "r"(ctx), "r"(idx), "r"(tl), "r"(th));
+ : "=&r" (msr), "=&r" (pid)
+ : "r" (ctx), "r" (idx), "r" (tl), "r" (th));
}
void
@@ -1406,7 +1406,7 @@ ppc4xx_tlb_init(void)
__asm volatile (
"mtspr %0,%1;"
"isync;"
- : : "K"(SPR_ZPR), "r"(0x1b000000));
+ : : "K" (SPR_ZPR), "r" (0x1b000000));
}
/*
@@ -1448,10 +1448,10 @@ ppc4xx_tlb_mapiodev(paddr_t base, psize_
/* tlb_nreserved is only allowed to grow, so this is safe. */
for (i = 0; i < tlb_nreserved; i++) {
__asm volatile (
- "tlbre %0,%2,1;" /* TLBLO */
- "tlbre %1,%2,0;" /* TLBHI */
- : "=&r"(lo), "=&r"(hi)
- : "r"(i));
+ "tlbre %0,%2,1;" /* TLBLO */
+ "tlbre %1,%2,0;" /* TLBHI */
+ : "=&r" (lo), "=&r" (hi)
+ : "r" (i));
KASSERT(hi & TLB_VALID);
KASSERT(mfspr(SPR_PID) == KERNEL_PID);
@@ -1503,11 +1503,11 @@ ppc4xx_tlb_reserve(paddr_t pa, vaddr_t v
lo |= TLB_I;
#endif
- __asm volatile(
+ __asm volatile (
"tlbwe %1,%0,1;" /* write TLBLO */
"tlbwe %2,%0,0;" /* write TLBHI */
"isync;"
- : : "r"(tlb_nreserved), "r"(lo), "r"(hi));
+ : : "r" (tlb_nreserved), "r" (lo), "r" (hi));
tlb_nreserved++;
}
Index: src/sys/arch/powerpc/ibm4xx/trap.c
diff -u src/sys/arch/powerpc/ibm4xx/trap.c:1.100 src/sys/arch/powerpc/ibm4xx/trap.c:1.101
--- src/sys/arch/powerpc/ibm4xx/trap.c:1.100 Tue Oct 4 13:45:50 2022
+++ src/sys/arch/powerpc/ibm4xx/trap.c Wed Oct 5 08:18:00 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.100 2022/10/04 13:45:50 rin Exp $ */
+/* $NetBSD: trap.c,v 1.101 2022/10/05 08:18:00 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -69,7 +69,7 @@
#define __UFETCHSTORE_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.100 2022/10/04 13:45:50 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.101 2022/10/05 08:18:00 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ddb.h"
@@ -452,7 +452,7 @@ copyin(const void *uaddr, void *kaddr, s
ctx = pm->pm_ctx;
}
- __asm volatile(
+ __asm volatile (
"mfmsr %[msr];" /* Save MSR */
"li %[tmp],0x20;" /* Disable IMMU */
"andc %[tmp],%[msr],%[tmp];"
@@ -571,7 +571,7 @@ copyout(const void *kaddr, void *uaddr,
ctx = pm->pm_ctx;
}
- __asm volatile(
+ __asm volatile (
"mfmsr %[msr];" /* Save MSR */
"li %[tmp],0x20;" /* Disable IMMU */
"andc %[tmp],%[msr],%[tmp];"
