Module Name: src
Committed By: msaitoh
Date: Thu Oct 6 00:22:16 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/dev/nvmm/x86: nvmm_x86.c
Log Message:
Update some AMD CPUID bits:
- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
To generate a diff of this commit:
cvs rdiff -u -r1.191 -r1.192 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.22 -r1.23 src/sys/dev/nvmm/x86/nvmm_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.191 src/sys/arch/x86/include/specialreg.h:1.192
--- src/sys/arch/x86/include/specialreg.h:1.191 Wed Jun 15 16:25:33 2022
+++ src/sys/arch/x86/include/specialreg.h Thu Oct 6 00:22:16 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.191 2022/06/15 16:25:33 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.192 2022/10/06 00:22:16 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -483,7 +483,7 @@
/* %ecx = 0, %edx */
#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */
#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */
-#define CPUID_SEF_FSREP_MOV __BIT(4) /* Fast Short REP MOVE */
+#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */
#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */
#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */
@@ -503,7 +503,7 @@
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
- "\5" "FSREP_MOV" \
+ "\5" "FSRM" \
"\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" \
"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
"\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \
@@ -527,7 +527,7 @@
"\31" "LAM"
/* %ecx = 1, %ebx */
-#define CPUID_SEF_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */
+#define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */
#define CPUID_SEF1_FLAGS_B "\20" \
"\1" "PPIN"
@@ -618,10 +618,10 @@
*/
/* %ecx = 1, %eax */
-#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
-#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
-#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
-#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
+#define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */
+#define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */
+#define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */
+#define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */
#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
@@ -801,6 +801,7 @@
#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
+#define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */
#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
@@ -812,26 +813,28 @@
#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */
#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
+#define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */
#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
+#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
- "\5RDPRU" "\7B6" \
+ "\5RDPRU" "\7MBE" \
"\11MCOMMIT" "\12WBNOINVD" "\13B10" \
"\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \
"\24IBRS_SAMEMODE" \
- "\25EFER_LSMSLE_UN" \
- "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" \
+ "\25EFER_LSMSLE_UN" "\30PPIN" \
+ "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \
"\35PSFD"
/* %ecx */
-#define CPUID_CAPEX_PerfTscSize __BITS(17,16)
-#define CPUID_CAPEX_ApicIdSize __BITS(15,12)
-#define CPUID_CAPEX_NC __BITS(7,0)
+#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */
+#define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */
+#define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */
/*
* AMD SVM Revision and Feature.
@@ -858,6 +861,7 @@
#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
+#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
#define CPUID_AMD_SVM_FLAGS "\20" \
@@ -867,9 +871,9 @@
"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
"\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
"\20" "V_VMSAVE_VMLOAD" \
- "\21" "VGIF" "\22" "GMET" "\24SSSCHECK" \
- "\25" "SPEC_CTRL" \
- "\31" "TLBICTL" \
+ "\21" "VGIF" "\22" "GMET" "\23B18" "\24SSSCHECK" \
+ "\25" "SPEC_CTRL" "\30HOST_MCE_OVERRIDE" \
+ "\31" "TLBICTL" "\32B25" "\32B26" "\32B27" \
"\35B28"
/*
Index: src/sys/dev/nvmm/x86/nvmm_x86.c
diff -u src/sys/dev/nvmm/x86/nvmm_x86.c:1.22 src/sys/dev/nvmm/x86/nvmm_x86.c:1.23
--- src/sys/dev/nvmm/x86/nvmm_x86.c:1.22 Sat Aug 20 23:13:51 2022
+++ src/sys/dev/nvmm/x86/nvmm_x86.c Thu Oct 6 00:22:16 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86.c,v 1.22 2022/08/20 23:13:51 riastradh Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.23 2022/10/06 00:22:16 msaitoh Exp $ */
/*
* Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.22 2022/08/20 23:13:51 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.23 2022/10/06 00:22:16 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -353,7 +353,7 @@ const struct nvmm_x86_cpuid_mask nvmm_cp
.edx =
/* CPUID_SEF_AVX512_4VNNIW excluded */
/* CPUID_SEF_AVX512_4FMAPS excluded */
- CPUID_SEF_FSREP_MOV |
+ CPUID_SEF_FSRM |
/* CPUID_SEF_AVX512_VP2INTERSECT excluded */
/* CPUID_SEF_SRBDS_CTRL excluded */
CPUID_SEF_MD_CLEAR |
