Module Name: src
Committed By: andvar
Date: Fri Oct 7 22:30:48 UTC 2022
Modified Files:
src/sys/arch/arm/omap: omapl1x_timer.c
Log Message:
fix typos in chained/unchained mode definitions (s/CHANINED/CHAINED).
fix typo in comment s/32 bot/32-bit/.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/omap/omapl1x_timer.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/omap/omapl1x_timer.c
diff -u src/sys/arch/arm/omap/omapl1x_timer.c:1.4 src/sys/arch/arm/omap/omapl1x_timer.c:1.5
--- src/sys/arch/arm/omap/omapl1x_timer.c:1.4 Sat Feb 12 17:09:43 2022
+++ src/sys/arch/arm/omap/omapl1x_timer.c Fri Oct 7 22:30:48 2022
@@ -25,7 +25,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omapl1x_timer.c,v 1.4 2022/02/12 17:09:43 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omapl1x_timer.c,v 1.5 2022/10/07 22:30:48 andvar Exp $");
#include "opt_timer.h"
@@ -117,9 +117,9 @@ static struct omapl1xtmr_softc *ref_sc;
/* Timer modes */
#define TGCR_TIMMODE_64BIT 0x0
-#define TGCR_TIMMODE_32BIT_UNCHANINED 0x1
+#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
#define TGCR_TIMMODE_64BIT_WDOG 0x2
-#define TGCR_TIMMODE_32BIT_CHANINED 0x3
+#define TGCR_TIMMODE_32BIT_CHAINED 0x3
#define TGCR_TIMMODE_SHIFT 2
#define TGCR_RS_STOP 0x0
@@ -277,8 +277,8 @@ timer_init (struct omapl1xtmr_softc *sc,
if (intr)
omapl1xtimer_prd_intr_enb(sc);
- /* Set timers to 32 bot unchained mode */
- val = TGCR_TIMMODE_32BIT_UNCHANINED << TGCR_TIMMODE_SHIFT;
+ /* Set timers to 32-bit unchained mode */
+ val = TGCR_TIMMODE_32BIT_UNCHAINED << TGCR_TIMMODE_SHIFT;
bus_space_write_4(sc->sc_iot, sc->sc_ioh, TGCR, val);
omapl1xtimer_start(sc);
