Module Name: src
Committed By: simonb
Date: Sat Oct 15 06:41:44 UTC 2022
Modified Files:
src/sys/arch/riscv/include: cpu_counter.h pmap.h pte.h sysreg.h
src/sys/arch/riscv/riscv: pmap_machdep.c riscv_machdep.c trap.c
Log Message:
#define<tab>
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/include/cpu_counter.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/include/pmap.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/pte.h
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/riscv/pmap_machdep.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/riscv/riscv/riscv_machdep.c
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/cpu_counter.h
diff -u src/sys/arch/riscv/include/cpu_counter.h:1.1 src/sys/arch/riscv/include/cpu_counter.h:1.2
--- src/sys/arch/riscv/include/cpu_counter.h:1.1 Fri Sep 19 17:36:26 2014
+++ src/sys/arch/riscv/include/cpu_counter.h Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_counter.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.2 2022/10/15 06:41:43 simonb Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
@@ -25,7 +25,7 @@
* SUCH DAMAGE.
*/
-/* $NetBSD: cpu_counter.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
+/* $NetBSD: cpu_counter.h,v 1.2 2022/10/15 06:41:43 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -56,7 +56,7 @@
*/
#ifndef _RISCV_CPU_COUNTER_H_
-#define _RISCV_CPU_COUNTER_H_
+#define _RISCV_CPU_COUNTER_H_
/*
* Machine-specific support for CPU counter.
@@ -67,7 +67,7 @@
#ifdef _KERNEL
#define cpu_hascounter() true
-#define cpu_counter() cpu_counter32()
+#define cpu_counter() cpu_counter32()
static __inline uint32_t
cpu_counter32(void)
Index: src/sys/arch/riscv/include/pmap.h
diff -u src/sys/arch/riscv/include/pmap.h:1.10 src/sys/arch/riscv/include/pmap.h:1.11
--- src/sys/arch/riscv/include/pmap.h:1.10 Tue Sep 20 07:18:23 2022
+++ src/sys/arch/riscv/include/pmap.h Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.10 2022/09/20 07:18:23 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.11 2022/10/15 06:41:43 simonb Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
*/
#ifndef _RISCV_PMAP_H_
-#define _RISCV_PMAP_H_
+#define _RISCV_PMAP_H_
#ifdef _KERNEL_OPT
#include "opt_modular.h"
@@ -50,57 +50,57 @@
#include <riscv/pte.h>
#include <riscv/sysreg.h>
-#define PMAP_SEGTABSIZE NPTEPG
-#define PMAP_PDETABSIZE NPTEPG
+#define PMAP_SEGTABSIZE NPTEPG
+#define PMAP_PDETABSIZE NPTEPG
#ifdef _LP64
-#define PTPSHIFT 3
+#define PTPSHIFT 3
/* This is SV48. */
//#define SEGLENGTH + SEGSHIFT + SEGSHIFT */
/* This is SV39. */
-#define XSEGSHIFT (SEGSHIFT + SEGLENGTH)
-#define NBXSEG (1ULL << XSEGSHIFT)
-#define XSEGOFSET (NBXSEG - 1) /* byte offset into xsegment */
-#define XSEGLENGTH (PGSHIFT - 3)
-#define NXSEGPG (1 << XSEGLENGTH)
+#define XSEGSHIFT (SEGSHIFT + SEGLENGTH)
+#define NBXSEG (1ULL << XSEGSHIFT)
+#define XSEGOFSET (NBXSEG - 1) /* byte offset into xsegment */
+#define XSEGLENGTH (PGSHIFT - 3)
+#define NXSEGPG (1 << XSEGLENGTH)
#else
-#define PTPSHIFT 2
-#define XSEGSHIFT SEGLENGTH
+#define PTPSHIFT 2
+#define XSEGSHIFT SEGLENGTH
#endif
-#define SEGLENGTH (PGSHIFT - PTPSHIFT)
-#define SEGSHIFT (SEGLENGTH + PGSHIFT)
-#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
-#define SEGOFSET (NBSEG - 1) /* byte offset into segment */
+#define SEGLENGTH (PGSHIFT - PTPSHIFT)
+#define SEGSHIFT (SEGLENGTH + PGSHIFT)
+#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
+#define SEGOFSET (NBSEG - 1) /* byte offset into segment */
-#define KERNEL_PID 0
+#define KERNEL_PID 0
-#define PMAP_HWPAGEWALKER 1
-#define PMAP_TLB_MAX 1
+#define PMAP_HWPAGEWALKER 1
+#define PMAP_TLB_MAX 1
#ifdef _LP64
-#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
-#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
+#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
+#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)(VM_MIN_KERNEL_ADDRESS - PAGE_SIZE))
#else
-#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)0xdeadbeef)
-#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)0xdeadbeef)
+#define PMAP_INVALID_PDETAB_ADDRESS ((pmap_pdetab_t *)0xdeadbeef)
+#define PMAP_INVALID_SEGTAB_ADDRESS ((pmap_segtab_t *)0xdeadbeef)
#endif
-#define PMAP_TLB_NUM_PIDS (__SHIFTOUT_MASK(SATP_ASID) + 1)
-#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
-#define PMAP_TLB_FLUSH_ASID_ON_RESET false
+#define PMAP_TLB_NUM_PIDS (__SHIFTOUT_MASK(SATP_ASID) + 1)
+#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
+#define PMAP_TLB_FLUSH_ASID_ON_RESET false
-#define pmap_phys_address(x) (x)
+#define pmap_phys_address(x) (x)
#ifndef __BSD_PTENTRY_T__
-#define __BSD_PTENTRY_T__
+#define __BSD_PTENTRY_T__
#ifdef _LP64
-#define PRIxPTE PRIx64
+#define PRIxPTE PRIx64
#else
-#define PRIxPTE PRIx32
+#define PRIxPTE PRIx32
#endif
#endif /* __BSD_PTENTRY_T__ */
-#define PMAP_NEED_PROCWR
+#define PMAP_NEED_PROCWR
static inline void
pmap_procwr(struct proc *p, vaddr_t va, vsize_t len)
{
@@ -110,12 +110,12 @@ pmap_procwr(struct proc *p, vaddr_t va,
#include <uvm/pmap/tlb.h>
#include <uvm/pmap/pmap_tlb.h>
-#define PMAP_GROWKERNEL
-#define PMAP_STEAL_MEMORY
+#define PMAP_GROWKERNEL
+#define PMAP_STEAL_MEMORY
#ifdef _KERNEL
-#define __HAVE_PMAP_MD
+#define __HAVE_PMAP_MD
struct pmap_md {
paddr_t md_ppn;
pd_entry_t *md_pdetab;
@@ -140,11 +140,11 @@ void pmap_bootstrap(vaddr_t kstart, vadd
extern vaddr_t pmap_direct_base;
extern vaddr_t pmap_direct_end;
-#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa))
-#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - pmap_direct_base)
+#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa))
+#define PMAP_DIRECT_UNMAP(va) ((paddr_t)(va) - pmap_direct_base)
-#define MEGAPAGE_TRUNC(x) ((x) & ~SEGOFSET)
-#define MEGAPAGE_ROUND(x) MEGAPAGE_TRUNC((x) + SEGOFSET)
+#define MEGAPAGE_TRUNC(x) ((x) & ~SEGOFSET)
+#define MEGAPAGE_ROUND(x) MEGAPAGE_TRUNC((x) + SEGOFSET)
#ifdef __PMAP_PRIVATE
@@ -199,7 +199,7 @@ pmap_md_tlb_asid_max(void)
* whether we are using modules or not.
*/
#ifndef __HAVE_VM_PAGE_MD
-#define __HAVE_VM_PAGE_MD
+#define __HAVE_VM_PAGE_MD
struct vm_page_md {
uintptr_t mdpg_dummy[3];
Index: src/sys/arch/riscv/include/pte.h
diff -u src/sys/arch/riscv/include/pte.h:1.8 src/sys/arch/riscv/include/pte.h:1.9
--- src/sys/arch/riscv/include/pte.h:1.8 Fri Sep 30 06:23:58 2022
+++ src/sys/arch/riscv/include/pte.h Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.8 2022/09/30 06:23:58 skrll Exp $ */
+/* $NetBSD: pte.h,v 1.9 2022/10/15 06:41:43 simonb Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -31,30 +31,30 @@
*/
#ifndef _RISCV_PTE_H_
-#define _RISCV_PTE_H_
+#define _RISCV_PTE_H_
#ifdef _LP64 /* Sv39 */
-#define PTE_PPN __BITS(53, 10)
+#define PTE_PPN __BITS(53, 10)
#define PTE_PPN0 __BITS(18, 10)
#define PTE_PPN1 __BITS(27, 19)
#define PTE_PPN2 __BITS(53, 28)
typedef uint64_t pt_entry_t;
typedef uint64_t pd_entry_t;
-#define atomic_cas_pte atomic_cas_64
+#define atomic_cas_pte atomic_cas_64
#else /* Sv32 */
-#define PTE_PPN __BITS(31, 10)
+#define PTE_PPN __BITS(31, 10)
#define PTE_PPN0 __BITS(19, 10)
#define PTE_PPN1 __BITS(31, 20)
typedef uint32_t pt_entry_t;
typedef uint32_t pd_entry_t;
-#define atomic_cas_pte atomic_cas_32
+#define atomic_cas_pte atomic_cas_32
#endif
-#define PTE_PPN_SHIFT 10
+#define PTE_PPN_SHIFT 10
-#define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t))
-#define NSEGPG NPTEPG
-#define NPDEPG NPTEPG
+#define NPTEPG (PAGE_SIZE / sizeof(pt_entry_t))
+#define NSEGPG NPTEPG
+#define NPDEPG NPTEPG
/* Software PTE bits. */
#define PTE_RSW __BITS(9,8)
@@ -71,13 +71,13 @@ typedef uint32_t pd_entry_t;
#define PTE_R __BIT(1) // Read
#define PTE_V __BIT(0) // Valid
-#define PTE_HARDWIRED (PTE_A | PTE_D)
-#define PTE_KERN (PTE_V | PTE_G | PTE_A | PTE_D)
-#define PTE_RW (PTE_R | PTE_W)
-#define PTE_RX (PTE_R | PTE_X)
+#define PTE_HARDWIRED (PTE_A | PTE_D)
+#define PTE_KERN (PTE_V | PTE_G | PTE_A | PTE_D)
+#define PTE_RW (PTE_R | PTE_W)
+#define PTE_RX (PTE_R | PTE_X)
-#define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT)
-#define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
+#define PA_TO_PTE(pa) (((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT)
+#define PTE_TO_PA(pte) (((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
#define L2_SHIFT 30
#define L1_SHIFT 21
@@ -94,9 +94,9 @@ typedef uint32_t pd_entry_t;
#define Ln_ENTRIES (1 << 9)
#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
-#define pl2_i(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
-#define pl1_i(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
-#define pl0_i(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)
+#define pl2_i(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
+#define pl1_i(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
+#define pl0_i(va) (((va) >> L0_SHIFT) & Ln_ADDR_MASK)
static inline const size_t
pte_index(vaddr_t va)
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.14 src/sys/arch/riscv/include/sysreg.h:1.15
--- src/sys/arch/riscv/include/sysreg.h:1.14 Sat Sep 10 09:28:26 2022
+++ src/sys/arch/riscv/include/sysreg.h Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.14 2022/09/10 09:28:26 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.15 2022/10/15 06:41:43 simonb Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#ifndef _RISCV_SYSREG_H_
-#define _RISCV_SYSREG_H_
+#define _RISCV_SYSREG_H_
#ifndef _KERNEL
#include <sys/param.h>
@@ -38,20 +38,20 @@
#include <riscv/reg.h>
-#define FCSR_FMASK 0 // no exception bits
-#define FCSR_FRM __BITS(7,5)
-#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
-#define FCSR_FRM_RTZ 0b001 // Round Towards Zero
-#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
-#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
-#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
-#define FCSR_FRM_DYN 0b111 // Dynamic rounding
-#define FCSR_FFLAGS __BITS(4,0) // Sticky bits
-#define FCSR_NV __BIT(4) // iNValid operation
-#define FCSR_DZ __BIT(3) // Divide by Zero
-#define FCSR_OF __BIT(2) // OverFlow
-#define FCSR_UF __BIT(1) // UnderFlow
-#define FCSR_NX __BIT(0) // iNeXact
+#define FCSR_FMASK 0 // no exception bits
+#define FCSR_FRM __BITS(7,5)
+#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
+#define FCSR_FRM_RTZ 0b001 // Round Towards Zero
+#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
+#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
+#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
+#define FCSR_FRM_DYN 0b111 // Dynamic rounding
+#define FCSR_FFLAGS __BITS(4,0) // Sticky bits
+#define FCSR_NV __BIT(4) // iNValid operation
+#define FCSR_DZ __BIT(3) // Divide by Zero
+#define FCSR_OF __BIT(2) // OverFlow
+#define FCSR_UF __BIT(1) // UnderFlow
+#define FCSR_NX __BIT(0) // iNeXact
static inline uint32_t
riscvreg_fcsr_read(void)
@@ -106,67 +106,67 @@ riscvreg_fcsr_write_frm(uint32_t __new)
/* Supervisor Status Register */
#ifdef _LP64
-#define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \
+#define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \
__BITS(12,9) | __BITS(7,6) | __BITS(3,2)
-#define SR_SD __BIT(63)
+#define SR_SD __BIT(63)
/* Bits 62-34 are WPRI */
-#define SR_UXL __BITS(33,32)
-#define SR_UXL_32 1
-#define SR_UXL_64 2
-#define SR_UXL_128 3
+#define SR_UXL __BITS(33,32)
+#define SR_UXL_32 1
+#define SR_UXL_64 2
+#define SR_UXL_128 3
/* Bits 31-20 are WPRI*/
#else
-#define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \
+#define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \
__BITS(7,6) | __BITS(3,2)
-#define SR_SD __BIT(31)
+#define SR_SD __BIT(31)
/* Bits 30-20 are WPRI*/
#endif /* _LP64 */
/* Both RV32 and RV64 have the bottom 20 bits shared */
-#define SR_MXR __BIT(19)
-#define SR_SUM __BIT(18)
+#define SR_MXR __BIT(19)
+#define SR_SUM __BIT(18)
/* Bit 17 is WPRI */
-#define SR_XS __BITS(16,15)
-#define SR_FS __BITS(14,13)
-#define SR_FS_OFF 0
-#define SR_FS_INITIAL 1
-#define SR_FS_CLEAN 2
-#define SR_FS_DIRTY 3
+#define SR_XS __BITS(16,15)
+#define SR_FS __BITS(14,13)
+#define SR_FS_OFF 0
+#define SR_FS_INITIAL 1
+#define SR_FS_CLEAN 2
+#define SR_FS_DIRTY 3
/* Bits 12-9 are WPRI */
-#define SR_SPP __BIT(8)
+#define SR_SPP __BIT(8)
/* Bits 7-6 are WPRI */
-#define SR_SPIE __BIT(5)
-#define SR_UPIE __BIT(4)
+#define SR_SPIE __BIT(5)
+#define SR_UPIE __BIT(4)
/* Bits 3-2 are WPRI */
-#define SR_SIE __BIT(1)
-#define SR_UIE __BIT(0)
+#define SR_SIE __BIT(1)
+#define SR_UIE __BIT(0)
/* Supervisor interrupt registers */
/* ... interrupt pending register (sip) */
/* Bit (XLEN-1)-10 is WIRI */
-#define SIP_SEIP __BIT(9)
-#define SIP_UEIP __BIT(8)
+#define SIP_SEIP __BIT(9)
+#define SIP_UEIP __BIT(8)
/* Bit 7-6 is WIRI */
-#define SIP_STIP __BIT(5)
-#define SIP_UTIP __BIT(4)
+#define SIP_STIP __BIT(5)
+#define SIP_UTIP __BIT(4)
/* Bit 3-2 is WIRI */
-#define SIP_SSIP __BIT(1)
-#define SIP_USIP __BIT(0)
+#define SIP_SSIP __BIT(1)
+#define SIP_USIP __BIT(0)
/* ... interrupt-enable register (sie) */
/* Bit (XLEN-1) - 10 is WIRI */
-#define SIE_SEIE __BIT(9)
-#define SIE_UEIE __BIT(8)
+#define SIE_SEIE __BIT(9)
+#define SIE_UEIE __BIT(8)
/* Bit 7-6 is WIRI */
-#define SIE_STIE __BIT(5)
-#define SIE_UTIE __BIT(4)
+#define SIE_STIE __BIT(5)
+#define SIE_UTIE __BIT(4)
/* Bit 3-2 is WIRI */
-#define SIE_SSIE __BIT(1)
-#define SIE_USIE __BIT(0)
+#define SIE_SSIE __BIT(1)
+#define SIE_USIE __BIT(0)
/* Mask for all interrupts */
-#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
+#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
#ifdef _LP64
#define SR_USER (SR_UIE)
@@ -210,23 +210,23 @@ riscvreg_status_set(uint32_t __mask)
}
// Cause register
-#define CAUSE_FETCH_MISALIGNED 0
-#define CAUSE_FETCH_ACCESS 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_BREAKPOINT 3
-#define CAUSE_LOAD_MISALIGNED 4
-#define CAUSE_LOAD_ACCESS 5
-#define CAUSE_STORE_MISALIGNED 6
-#define CAUSE_STORE_ACCESS 7
-#define CAUSE_SYSCALL 8
-#define CAUSE_USER_ECALL 8
-#define CAUSE_SUPERVISOR_ECALL 9
+#define CAUSE_FETCH_MISALIGNED 0
+#define CAUSE_FETCH_ACCESS 1
+#define CAUSE_ILLEGAL_INSTRUCTION 2
+#define CAUSE_BREAKPOINT 3
+#define CAUSE_LOAD_MISALIGNED 4
+#define CAUSE_LOAD_ACCESS 5
+#define CAUSE_STORE_MISALIGNED 6
+#define CAUSE_STORE_ACCESS 7
+#define CAUSE_SYSCALL 8
+#define CAUSE_USER_ECALL 8
+#define CAUSE_SUPERVISOR_ECALL 9
/* 10 is reserved */
-#define CAUSE_MACHINE_ECALL 11
-#define CAUSE_FETCH_PAGE_FAULT 12
-#define CAUSE_LOAD_PAGE_FAULT 13
+#define CAUSE_MACHINE_ECALL 11
+#define CAUSE_FETCH_PAGE_FAULT 12
+#define CAUSE_LOAD_PAGE_FAULT 13
/* 14 is Reserved */
-#define CAUSE_STORE_PAGE_FAULT 15
+#define CAUSE_STORE_PAGE_FAULT 15
/* >= 16 is reserved */
static inline uint64_t
@@ -252,16 +252,16 @@ riscvreg_cycle_read(void)
}
#ifdef _LP64
-#define SATP_MODE __BITS(63,60)
-#define SATP_MODE_SV39 8
-#define SATP_MODE_SV48 9
-#define SATP_ASID __BITS(59,44)
-#define SATP_PPN __BITS(43,0)
+#define SATP_MODE __BITS(63,60)
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_ASID __BITS(59,44)
+#define SATP_PPN __BITS(43,0)
#else
-#define SATP_MODE __BIT(31)
-#define SATP_MODE_SV32 1
-#define SATP_ASID __BITS(30,22)
-#define SATP_PPN __BITS(21,0)
+#define SATP_MODE __BIT(31)
+#define SATP_MODE_SV32 1
+#define SATP_ASID __BITS(30,22)
+#define SATP_PPN __BITS(21,0)
#endif
static inline uintptr_t
Index: src/sys/arch/riscv/riscv/pmap_machdep.c
diff -u src/sys/arch/riscv/riscv/pmap_machdep.c:1.11 src/sys/arch/riscv/riscv/pmap_machdep.c:1.12
--- src/sys/arch/riscv/riscv/pmap_machdep.c:1.11 Tue Sep 20 07:18:23 2022
+++ src/sys/arch/riscv/riscv/pmap_machdep.c Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap_machdep.c,v 1.11 2022/09/20 07:18:23 skrll Exp $ */
+/* $NetBSD: pmap_machdep.c,v 1.12 2022/10/15 06:41:43 simonb Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -32,10 +32,10 @@
#include "opt_riscv_debug.h"
-#define __PMAP_PRIVATE
+#define __PMAP_PRIVATE
#include <sys/cdefs.h>
-__RCSID("$NetBSD: pmap_machdep.c,v 1.11 2022/09/20 07:18:23 skrll Exp $");
+__RCSID("$NetBSD: pmap_machdep.c,v 1.12 2022/10/15 06:41:43 simonb Exp $");
#include <sys/param.h>
#include <sys/buf.h>
@@ -46,9 +46,9 @@ __RCSID("$NetBSD: pmap_machdep.c,v 1.11
#include <riscv/sysreg.h>
#ifdef VERBOSE_INIT_RISCV
-#define VPRINTF(...) printf(__VA_ARGS__)
+#define VPRINTF(...) printf(__VA_ARGS__)
#else
-#define VPRINTF(...) __nothing
+#define VPRINTF(...) __nothing
#endif
int riscv_poolpage_vmfreelist = VM_FREELIST_DEFAULT;
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.19 src/sys/arch/riscv/riscv/riscv_machdep.c:1.20
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.19 Wed Sep 28 06:05:28 2022
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.19 2022/09/28 06:05:28 skrll Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.20 2022/10/15 06:41:43 simonb Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
#include "opt_riscv_debug.h"
#include <sys/cdefs.h>
-__RCSID("$NetBSD: riscv_machdep.c,v 1.19 2022/09/28 06:05:28 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.20 2022/10/15 06:41:43 simonb Exp $");
#include <sys/param.h>
@@ -66,13 +66,13 @@ char machine_arch[] = MACHINE_ARCH;
#include <dev/fdt/fdt_memory.h>
#ifdef VERBOSE_INIT_RISCV
-#define VPRINTF(...) printf(__VA_ARGS__)
+#define VPRINTF(...) printf(__VA_ARGS__)
#else
-#define VPRINTF(...) __nothing
+#define VPRINTF(...) __nothing
#endif
#ifndef FDT_MAX_BOOT_STRING
-#define FDT_MAX_BOOT_STRING 1024
+#define FDT_MAX_BOOT_STRING 1024
#endif
char bootargs[FDT_MAX_BOOT_STRING] = "";
@@ -532,7 +532,7 @@ init_riscv(register_t hartid, vaddr_t vd
kernelvmstart = kernend_mega;
-#define DPRINTF(v) VPRINTF("%24s = 0x%16lx\n", #v, (unsigned long)v);
+#define DPRINTF(v) VPRINTF("%24s = 0x%16lx\n", #v, (unsigned long)v);
VPRINTF("------------------------------------------\n");
DPRINTF(kern_vtopdiff);
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.18 src/sys/arch/riscv/riscv/trap.c:1.19
--- src/sys/arch/riscv/riscv/trap.c:1.18 Tue Sep 27 08:18:21 2022
+++ src/sys/arch/riscv/riscv/trap.c Sat Oct 15 06:41:43 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.18 2022/09/27 08:18:21 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.19 2022/10/15 06:41:43 simonb Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,10 +31,10 @@
#include <sys/cdefs.h>
-#define __PMAP_PRIVATE
-#define __UFETCHSTORE_PRIVATE
+#define __PMAP_PRIVATE
+#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.18 2022/09/27 08:18:21 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.19 2022/10/15 06:41:43 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
