Module Name: src
Committed By: skrll
Date: Thu Oct 20 06:58:38 UTC 2022
Modified Files:
src/sys/arch/arm/arm: bcopyinout.S bcopyinout_xscale.S blockio.S
copystr.S cpu_in_cksum.S cpufunc_asm_arm10.S cpufunc_asm_arm67.S
cpufunc_asm_arm7tdmi.S cpufunc_asm_arm8.S cpufunc_asm_arm9.S
cpufunc_asm_armv4.S cpufunc_asm_armv5.S cpufunc_asm_fa526.S
cpufunc_asm_pj4b.S cpufunc_asm_sa1.S cpufunc_asm_xscale.S vectors.S
Log Message:
Trailing whitespace.
To generate a diff of this commit:
cvs rdiff -u -r1.22 -r1.23 src/sys/arch/arm/arm/bcopyinout.S
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/arm/bcopyinout_xscale.S \
src/sys/arch/arm/arm/cpufunc_asm_arm10.S \
src/sys/arch/arm/arm/cpufunc_asm_arm9.S
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/arm/blockio.S \
src/sys/arch/arm/arm/cpufunc_asm_armv5.S
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/arm/copystr.S \
src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/arm/arm/cpu_in_cksum.S
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/arm/cpufunc_asm_arm67.S \
src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S \
src/sys/arch/arm/arm/cpufunc_asm_fa526.S
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/arm/cpufunc_asm_arm8.S \
src/sys/arch/arm/arm/vectors.S
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/arm/cpufunc_asm_armv4.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/arm/cpufunc_asm_sa1.S
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/arm/arm/cpufunc_asm_xscale.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/bcopyinout.S
diff -u src/sys/arch/arm/arm/bcopyinout.S:1.22 src/sys/arch/arm/arm/bcopyinout.S:1.23
--- src/sys/arch/arm/arm/bcopyinout.S:1.22 Fri Dec 11 09:14:19 2020
+++ src/sys/arch/arm/arm/bcopyinout.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bcopyinout.S,v 1.22 2020/12/11 09:14:19 dholland Exp $ */
+/* $NetBSD: bcopyinout.S,v 1.23 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -52,14 +52,14 @@
#include "bcopyinout_xscale.S"
#else
-RCSID("$NetBSD: bcopyinout.S,v 1.22 2020/12/11 09:14:19 dholland Exp $")
+RCSID("$NetBSD: bcopyinout.S,v 1.23 2022/10/20 06:58:38 skrll Exp $")
.text
.align 0
#define SAVE_REGS stmfd sp!, {r4-r11}
#define RESTORE_REGS ldmfd sp!, {r4-r11}
-
+
#if defined(__XSCALE__) || defined(_ARM_ARCH_6)
#define HELLOCPP #
#define PREFETCH(rx,o) pld [ rx , HELLOCPP (o) ]
@@ -78,7 +78,7 @@ RCSID("$NetBSD: bcopyinout.S,v 1.22 2020
* r4-r11 are scratch
*/
ENTRY(copyin)
- /* Quick exit if length is zero */
+ /* Quick exit if length is zero */
teq r2, #0
moveq r0, #0
RETc(eq)
@@ -291,7 +291,7 @@ END(copyin)
*/
ENTRY(copyout)
- /* Quick exit if length is zero */
+ /* Quick exit if length is zero */
teq r2, #0
moveq r0, #0
moveq pc, lr
@@ -494,7 +494,7 @@ END(copyout)
*/
ENTRY(kcopy)
- /* Quick exit if length is zero */
+ /* Quick exit if length is zero */
teq r2, #0
moveq r0, #0
moveq pc, lr
Index: src/sys/arch/arm/arm/bcopyinout_xscale.S
diff -u src/sys/arch/arm/arm/bcopyinout_xscale.S:1.11 src/sys/arch/arm/arm/bcopyinout_xscale.S:1.12
--- src/sys/arch/arm/arm/bcopyinout_xscale.S:1.11 Sun Dec 1 02:54:33 2013
+++ src/sys/arch/arm/arm/bcopyinout_xscale.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: bcopyinout_xscale.S,v 1.11 2013/12/01 02:54:33 joerg Exp $ */
+/* $NetBSD: bcopyinout_xscale.S,v 1.12 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -35,7 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-RCSID("$NetBSD: bcopyinout_xscale.S,v 1.11 2013/12/01 02:54:33 joerg Exp $")
+RCSID("$NetBSD: bcopyinout_xscale.S,v 1.12 2022/10/20 06:58:38 skrll Exp $")
.text
.align 0
@@ -292,10 +292,10 @@ ENTRY(copyin)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lcopyin_bad1:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyin_bad1_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -353,10 +353,10 @@ ENTRY(copyin)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lcopyin_bad2:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyin_bad2_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -414,10 +414,10 @@ ENTRY(copyin)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lcopyin_bad3:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyin_bad3_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -445,7 +445,7 @@ ENTRY(copyin)
pop {r4-r7}
mov r3, #0x00
adds r2, r2, #0x04
- RETc(eq)
+ RETc(eq)
.Lcopyin_l4_2:
rsbs r2, r2, #0x03
addne pc, pc, r2, lsl #3
@@ -732,10 +732,10 @@ ENTRY(copyout)
strt r6, [r1], #0x04
strt r7, [r1], #0x04
.Lcopyout_bad1:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyout_bad1_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -793,10 +793,10 @@ ENTRY(copyout)
strt r6, [r1], #0x04
strt r7, [r1], #0x04
.Lcopyout_bad2:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyout_bad2_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -854,10 +854,10 @@ ENTRY(copyout)
strt r6, [r1], #0x04
strt r7, [r1], #0x04
.Lcopyout_bad3:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lcopyout_bad3_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -1150,10 +1150,10 @@ ENTRY(kcopy)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lkcopy_bad1:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lkcopy_bad1_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -1211,10 +1211,10 @@ ENTRY(kcopy)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lkcopy_bad2:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lkcopy_bad2_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -1272,10 +1272,10 @@ ENTRY(kcopy)
str r6, [r1], #0x04
str r7, [r1], #0x04
.Lkcopy_bad3:
- subs r2, r2, #0x10
+ subs r2, r2, #0x10
bge .Lkcopy_bad3_loop16
- adds r2, r2, #0x10
+ adds r2, r2, #0x10
popeq {r4-r7}
RETc(eq) /* Return now if done */
subs r2, r2, #0x04
@@ -1303,7 +1303,7 @@ ENTRY(kcopy)
pop {r4-r7}
mov r3, #0x00
adds r2, r2, #0x04
- RETc(eq)
+ RETc(eq)
.Lkcopy_bad_endgame2:
rsbs r2, r2, #0x03
addne pc, pc, r2, lsl #3
Index: src/sys/arch/arm/arm/cpufunc_asm_arm10.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm10.S:1.11 src/sys/arch/arm/arm/cpufunc_asm_arm10.S:1.12
--- src/sys/arch/arm/arm/cpufunc_asm_arm10.S:1.11 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm10.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm10.S,v 1.11 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm10.S,v 1.12 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2002 ARM Limited
@@ -30,7 +30,7 @@
*
* ARM10 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include <machine/asm.h>
#include <arm/locore.h>
#include "assym.h"
Index: src/sys/arch/arm/arm/cpufunc_asm_arm9.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm9.S:1.11 src/sys/arch/arm/arm/cpufunc_asm_arm9.S:1.12
--- src/sys/arch/arm/arm/cpufunc_asm_arm9.S:1.11 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm9.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm9.S,v 1.11 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm9.S,v 1.12 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2001, 2004 ARM Limited
@@ -30,7 +30,7 @@
*
* ARM9 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
@@ -260,7 +260,7 @@ END(arm9_context_switch)
/*
* Parameters for the cache cleaning code. Note that the order of these
- * four variables is assumed in the code above. Hence the reason for
+ * four variables is assumed in the code above. Hence the reason for
* declaring them in the assembler file.
*/
.align 0
Index: src/sys/arch/arm/arm/blockio.S
diff -u src/sys/arch/arm/arm/blockio.S:1.8 src/sys/arch/arm/arm/blockio.S:1.9
--- src/sys/arch/arm/arm/blockio.S:1.8 Sun Aug 18 06:29:29 2013
+++ src/sys/arch/arm/arm/blockio.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: blockio.S,v 1.8 2013/08/18 06:29:29 matt Exp $ */
+/* $NetBSD: blockio.S,v 1.9 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2001 Ben Harris.
@@ -43,12 +43,12 @@
*
* Created : 08/10/94
* Modified : 22/01/99 -- R.Earnshaw
- * Faster, and small tweaks for StrongARM
+ * Faster, and small tweaks for StrongARM
*/
#include <machine/asm.h>
-RCSID("$NetBSD: blockio.S,v 1.8 2013/08/18 06:29:29 matt Exp $")
+RCSID("$NetBSD: blockio.S,v 1.9 2022/10/20 06:58:38 skrll Exp $")
/*
* Read bytes from an I/O address into a block of memory
@@ -250,7 +250,7 @@ ENTRY(outsw)
str r3, [r0]
str ip, [r0]
-
+
/* mov ip, r3, lsl #16
* orr ip, ip, ip, lsr #16
* str ip, [r0]
@@ -358,7 +358,7 @@ ENTRY(outsw16)
eor r3, r3, r4, lsl #16 /* r3 = (A^B^A)(B) = (B)(B) */
str r3, [r0]
str r4, [r0]
-
+
/* mov r3, r4, lsl #16
* orr r3, r3, r3, lsr #16
* str r3, [r0]
Index: src/sys/arch/arm/arm/cpufunc_asm_armv5.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.8 src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.9
--- src/sys/arch/arm/arm/cpufunc_asm_armv5.S:1.8 Thu Oct 7 09:57:27 2021
+++ src/sys/arch/arm/arm/cpufunc_asm_armv5.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv5.S,v 1.8 2021/10/07 09:57:27 rin Exp $ */
+/* $NetBSD: cpufunc_asm_armv5.S,v 1.9 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2002, 2005 ARM Limited
@@ -228,7 +228,7 @@ ENTRY(armv5_dcache_wbinv_all)
/*
* Parameters for the cache cleaning code. Note that the order of these
- * four variables is assumed in the code above. Hence the reason for
+ * four variables is assumed in the code above. Hence the reason for
* declaring them in the assembler file.
*/
.align 0
Index: src/sys/arch/arm/arm/copystr.S
diff -u src/sys/arch/arm/arm/copystr.S:1.13 src/sys/arch/arm/arm/copystr.S:1.14
--- src/sys/arch/arm/arm/copystr.S:1.13 Tue Jun 30 16:20:00 2020
+++ src/sys/arch/arm/arm/copystr.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: copystr.S,v 1.13 2020/06/30 16:20:00 maxv Exp $ */
+/* $NetBSD: copystr.S,v 1.14 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -40,14 +40,14 @@
#include "opt_multiprocessor.h"
#include "opt_cpuoptions.h"
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
-RCSID("$NetBSD: copystr.S,v 1.13 2020/06/30 16:20:00 maxv Exp $")
+RCSID("$NetBSD: copystr.S,v 1.14 2022/10/20 06:58:38 skrll Exp $")
#include <sys/errno.h>
Index: src/sys/arch/arm/arm/cpufunc_asm_pj4b.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.13 src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.14
--- src/sys/arch/arm/arm/cpufunc_asm_pj4b.S:1.13 Sat Jan 7 16:19:28 2017
+++ src/sys/arch/arm/arm/cpufunc_asm_pj4b.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_pj4b.S,v 1.13 2017/01/07 16:19:28 kiyohara Exp $ */
+/* $NetBSD: cpufunc_asm_pj4b.S,v 1.14 2022/10/20 06:58:38 skrll Exp $ */
/*******************************************************************************
Copyright (C) Marvell International Ltd. and its affiliates
@@ -81,7 +81,7 @@ ENTRY(pj4b_config)
orr r0, r0, #(1 << 25) @ Intervention Interleave disable
orr r0, r0, #(1 << 27) @ Critical word 1st sequencing dis.
orr r0, r0, #(1 << 29) @ Disable MO device R/W
- orr r0, r0, #(1 << 30) @ L1 cache strict round-robin
+ orr r0, r0, #(1 << 30) @ L1 cache strict round-robin
orr r0, r0, #(1 << 31) @ Enable write evict
mcr p15, 1, r0, c15, c1, 2
@@ -91,7 +91,7 @@ ENTRY(pj4b_config)
tst ip, #PJ4B_MPIDR_MP
beq 1f @ if not set, not a MPCORE
tst ip, #PJ4B_MPIDR_U
- bne 1f @ if set, uni-processor system
+ bne 1f @ if set, uni-processor system
orr r0, r0, #(PJ4B_AUXFMC0_SMPNAMP) @ enable SMP/nAMP
orr r0, r0, #(PJ4B_AUXFMC0_FW) @ enable maintenance bcast
1:
Index: src/sys/arch/arm/arm/cpu_in_cksum.S
diff -u src/sys/arch/arm/arm/cpu_in_cksum.S:1.12 src/sys/arch/arm/arm/cpu_in_cksum.S:1.13
--- src/sys/arch/arm/arm/cpu_in_cksum.S:1.12 Wed Jan 24 09:04:44 2018
+++ src/sys/arch/arm/arm/cpu_in_cksum.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_in_cksum.S,v 1.12 2018/01/24 09:04:44 skrll Exp $ */
+/* $NetBSD: cpu_in_cksum.S,v 1.13 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
@@ -40,8 +40,8 @@
*/
#include <machine/asm.h>
-RCSID("$NetBSD: cpu_in_cksum.S,v 1.12 2018/01/24 09:04:44 skrll Exp $")
-
+RCSID("$NetBSD: cpu_in_cksum.S,v 1.13 2022/10/20 06:58:38 skrll Exp $")
+
#include "assym.h"
/*
@@ -61,7 +61,7 @@ RCSID("$NetBSD: cpu_in_cksum.S,v 1.12 20
/* LINTSTUB: Func: int cpu_in_cksum(struct mbuf *, int, int, uint32_t) */
ENTRY(cpu_in_cksum)
push {r4-r11,lr}
-
+
mov r8, r3 /* Accumulate sum in r8 */
mov r9, r1 /* save len in r9 */
mov ip, r0 /* set ip to the current mbuf */
@@ -78,7 +78,7 @@ ENTRY(cpu_in_cksum)
b .Lin_cksum_whoops
.Lin_cksum_skip_done:
- add r0, r2, r0 /* data += offset (offset is < 0) */
+ add r0, r2, r0 /* data += offset (offset is < 0) */
add r0, r0, r1 /* data += length of mbuf */
/* data == start of data to cksum */
rsb r1, r2, #0x00 /* length = remainder of mbuf to read */
Index: src/sys/arch/arm/arm/cpufunc_asm_arm67.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm67.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_arm67.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_arm67.S:1.7 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm67.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm67.S,v 1.7 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm67.S,v 1.8 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -34,7 +34,7 @@
*
* ARM6/ARM7 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
@@ -71,7 +71,7 @@ ENTRY(arm67_setttb)
* TLB functions
*/
ENTRY(arm67_tlb_flush)
- mcr p15, 0, r0, c5, c0, 0
+ mcr p15, 0, r0, c5, c0, 0
mov pc, lr
ENTRY(arm67_tlb_purge)
Index: src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S:1.7 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm7tdmi.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.7 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm7tdmi.S,v 1.8 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2001 John Fremlin
@@ -33,7 +33,7 @@
*
* ARM7TDMI assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
Index: src/sys/arch/arm/arm/cpufunc_asm_fa526.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_fa526.S:1.7 src/sys/arch/arm/arm/cpufunc_asm_fa526.S:1.8
--- src/sys/arch/arm/arm/cpufunc_asm_fa526.S:1.7 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_fa526.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_fa526.S,v 1.7 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_fa526.S,v 1.8 2022/10/20 06:58:38 skrll Exp $ */
/*-
* Copyright (c) 2008 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -43,7 +43,7 @@ ENTRY(fa526_setttb)
mcr p15, 0, r2, c7, c5, 6 /* invalidate BTB */
mcr p15, 0, r2, c7, c10, 4 /* drain write and fill buffer */
1:
- mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
+ mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
/* If we have updated the TTB we must flush the TLB */
mcrne p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
Index: src/sys/arch/arm/arm/cpufunc_asm_arm8.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.10 src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.11
--- src/sys/arch/arm/arm/cpufunc_asm_arm8.S:1.10 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_arm8.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_arm8.S,v 1.10 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_arm8.S,v 1.11 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 1997 ARM Limited
@@ -34,7 +34,7 @@
*
* ARM8 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
Index: src/sys/arch/arm/arm/vectors.S
diff -u src/sys/arch/arm/arm/vectors.S:1.10 src/sys/arch/arm/arm/vectors.S:1.11
--- src/sys/arch/arm/arm/vectors.S:1.10 Fri Sep 6 21:25:34 2013
+++ src/sys/arch/arm/arm/vectors.S Thu Oct 20 06:58:38 2022
@@ -1,9 +1,9 @@
-/* $NetBSD: vectors.S,v 1.10 2013/09/06 21:25:34 skrll Exp $ */
+/* $NetBSD: vectors.S,v 1.11 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (C) 1994-1997 Mark Brinicombe
* Copyright (C) 1994 Brini
- * All rights reserved.
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -18,10 +18,10 @@
* This product includes software developed by Brini.
* 4. The name of Brini may not be used to endorse or promote products
* derived from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
@@ -50,7 +50,7 @@
#if defined(CPU_ARMV7) || defined(CPU_ARM11) || defined(ARM_HAS_VBAR)
/*
* ARMv[67] processors with the Security Extension have the VBAR
- * which redirects the low vector to any 32-byte aligned address.
+ * which redirects the low vector to any 32-byte aligned address.
* Since we are in kernel, we can just do a relative branch to the
* exception code and avoid the intermediate load.
*/
Index: src/sys/arch/arm/arm/cpufunc_asm_armv4.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv4.S:1.5 src/sys/arch/arm/arm/cpufunc_asm_armv4.S:1.6
--- src/sys/arch/arm/arm/cpufunc_asm_armv4.S:1.5 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_armv4.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_armv4.S,v 1.5 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_armv4.S,v 1.6 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2001 ARM Limited
@@ -35,7 +35,7 @@
*
* ARMv4 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <machine/asm.h>
#include <arm/locore.h>
Index: src/sys/arch/arm/arm/cpufunc_asm_sa1.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.15 src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.16
--- src/sys/arch/arm/arm/cpufunc_asm_sa1.S:1.15 Sun Mar 30 01:15:03 2014
+++ src/sys/arch/arm/arm/cpufunc_asm_sa1.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_sa1.S,v 1.15 2014/03/30 01:15:03 matt Exp $ */
+/* $NetBSD: cpufunc_asm_sa1.S,v 1.16 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 1997,1998 Mark Brinicombe.
@@ -34,7 +34,7 @@
*
* SA-1 assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <arm/asm.h>
#include <arm/locore.h>
@@ -56,7 +56,7 @@ ENTRY(sa1_setttb)
#else
ldr r3, .Lblock_userspace_access
ldr r2, [r3]
- orr ip, r2, #1
+ orr ip, r2, #1
str ip, [r3]
#endif
cmp r1, #0
@@ -68,7 +68,7 @@ ENTRY(sa1_setttb)
mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
cmp r0, #1
-1: /* Write the TTB */
+1: /* Write the TTB */
mcr p15, 0, r0, c2, c0, 0
/* If we have updated the TTB we must flush the TLB */
Index: src/sys/arch/arm/arm/cpufunc_asm_xscale.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.24 src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.25
--- src/sys/arch/arm/arm/cpufunc_asm_xscale.S:1.24 Wed Jan 17 02:37:32 2018
+++ src/sys/arch/arm/arm/cpufunc_asm_xscale.S Thu Oct 20 06:58:38 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc_asm_xscale.S,v 1.24 2018/01/17 02:37:32 christos Exp $ */
+/* $NetBSD: cpufunc_asm_xscale.S,v 1.25 2022/10/20 06:58:38 skrll Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -70,7 +70,7 @@
*
* XScale assembly functions for CPU / MMU / TLB specific operations
*/
-
+
#include "assym.h"
#include <arm/asm.h>
#include <arm/locore.h>
@@ -140,7 +140,7 @@ ENTRY(xscale_setttb)
#else
ldr r3, .Lblock_userspace_access
ldr r2, [r3]
- orr ip, r2, #1
+ orr ip, r2, #1
str ip, [r3]
#endif
cmp r1, #0 /* flush cache/TLB? */
@@ -155,7 +155,7 @@ ENTRY(xscale_setttb)
ldmfd sp!, {r0-r3, lr}
cmp r0, #1
-1: /* Write the TTB */
+1: /* Write the TTB */
mcr p15, 0, r0, c2, c0, 0
beq 2f /* nope, so don't */
