CVS commit: src/sys/arch/riscv/riscv

[Simon Burge]

Module Name:    src
Committed By:   simonb
Date:           Mon Oct 31 12:50:49 UTC 2022

Modified Files:
        src/sys/arch/riscv/riscv: bus_space_generic.S

Log Message:
In bus_space_write_{1,2,4,8} store the correct register in write to device.


To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/riscv/bus_space_generic.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.


Modified files:

Index: src/sys/arch/riscv/riscv/bus_space_generic.S
diff -u src/sys/arch/riscv/riscv/bus_space_generic.S:1.2 src/sys/arch/riscv/riscv/bus_space_generic.S:1.3
--- src/sys/arch/riscv/riscv/bus_space_generic.S:1.2	Mon Oct 31 12:49:18 2022
+++ src/sys/arch/riscv/riscv/bus_space_generic.S	Mon Oct 31 12:50:49 2022
@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $	*/
+/*	$NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $	*/
 
 /*-
  * Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #include <riscv/asm.h>
 #include "assym.h"
 
-RCSID("$NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $")
+RCSID("$NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $")
 
 
 /* void bs_c_1(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
@@ -245,7 +245,7 @@ ENTRY_NP(generic_bs_w_1)
 	PTR_L	a5, BS_STRIDE(a0)	/* stride */
 	PTR_SLL	a2, a2, a5		/* offset <<= stride */
 	PTR_ADD	a2, a2, a1		/* add to address */
-	sb	a0, 0(a2)		/* store 8-bit */
+	sb	a3, 0(a2)		/* store 8-bit */
 	ret
 END(generic_bs_w_1)
 
@@ -255,7 +255,7 @@ ENTRY_NP(generic_bs_w_2)
 	PTR_L	a5, BS_STRIDE(a0)	/* stride */
 	PTR_SLL	a2, a2, a5		/* offset <<= stride */
 	PTR_ADD	a2, a2, a1		/* add to address */
-	sh	a0 ,0(a2)		/* store 16-bit */
+	sh	a3 ,0(a2)		/* store 16-bit */
 	ret
 END(generic_bs_w_2)
 
@@ -265,7 +265,7 @@ ENTRY_NP(generic_bs_w_4)
 	PTR_L	a5, BS_STRIDE(a0)	/* stride */
 	PTR_SLL	a2, a2, a5		/* offset <<= stride */
 	PTR_ADD	a2, a2, a1		/* add to address */
-	sw	a0, 0(a2)		/* store 32-bit */
+	sw	a3, 0(a2)		/* store 32-bit */
 	ret
 END(generic_bs_w_4)
 
@@ -276,7 +276,7 @@ ENTRY_NP(generic_bs_w_8)
 	PTR_L	a5, BS_STRIDE(a0)	/* stride */
 	PTR_SLL	a2, a2, a5		/* offset <<= stride */
 	PTR_ADD	a2, a2, a1		/* add to address */
-	sd	a0, 0(a2)		/* store 64-bit */
+	sd	a3, 0(a2)		/* store 64-bit */
 	ret
 END(generic_bs_w_8)
 #endif