Module Name: src
Committed By: jmcneill
Date: Wed Nov 2 10:38:04 UTC 2022
Modified Files:
src/sys/dev/sdmmc: sdhc.c
Log Message:
Select DMA mode after programming the ADMA base address register(s).
The Arasan SDHCI 8.9a found in the Xilinx Zynq-7000 SoC requires this
sequence to avoid sporadic transfer errors.
To generate a diff of this commit:
cvs rdiff -u -r1.116 -r1.117 src/sys/dev/sdmmc/sdhc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/sdmmc/sdhc.c
diff -u src/sys/dev/sdmmc/sdhc.c:1.116 src/sys/dev/sdmmc/sdhc.c:1.117
--- src/sys/dev/sdmmc/sdhc.c:1.116 Fri Oct 14 07:54:49 2022
+++ src/sys/dev/sdmmc/sdhc.c Wed Nov 2 10:38:04 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: sdhc.c,v 1.116 2022/10/14 07:54:49 jmcneill Exp $ */
+/* $NetBSD: sdhc.c,v 1.117 2022/11/02 10:38:04 jmcneill Exp $ */
/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
/*
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.116 2022/10/14 07:54:49 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.117 2022/11/02 10:38:04 jmcneill Exp $");
#ifdef _KERNEL_OPT
#include "opt_sdmmc.h"
@@ -1835,21 +1835,21 @@ sdhc_start_command(struct sdhc_host *hp,
}
bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,
BUS_DMASYNC_PREWRITE);
- if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
- HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT);
- HSET4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT_ADMA2);
- } else {
- HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
- HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2);
- }
const bus_addr_t desc_addr = hp->adma_map->dm_segs[0].ds_addr;
-
HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR, desc_addr & 0xffffffff);
if (ISSET(hp->flags, SHF_USE_ADMA2_64)) {
HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR + 4,
(uint64_t)desc_addr >> 32);
}
+
+ if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
+ HCLR4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT);
+ HSET4(hp, SDHC_HOST_CTL, SDHC_USDHC_DMA_SELECT_ADMA2);
+ } else {
+ HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT);
+ HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA2);
+ }
} else if (ISSET(mode, SDHC_DMA_ENABLE) &&
!ISSET(sc->sc_flags, SDHC_FLAG_EXTERNAL_DMA)) {
if (ISSET(hp->sc->sc_flags, SDHC_FLAG_USDHC)) {
