Module Name: src
Committed By: msaitoh
Date: Wed Nov 16 14:55:50 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
To generate a diff of this commit:
cvs rdiff -u -r1.196 -r1.197 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.130 -r1.131 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.196 src/sys/arch/x86/include/specialreg.h:1.197
--- src/sys/arch/x86/include/specialreg.h:1.196 Wed Nov 16 14:01:41 2022
+++ src/sys/arch/x86/include/specialreg.h Wed Nov 16 14:55:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.196 2022/11/16 14:01:41 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.197 2022/11/16 14:55:50 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -1009,6 +1009,24 @@
"\22CpuidUserDis"
/*
+ * AMD Extended Performance Monitoring and Debug
+ * CPUID Fn8000_0022
+ */
+
+/* %eax */
+#define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */
+#define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */
+#define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */
+
+#define CPUID_AXPERF_FLAGS "\20" \
+ "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze"
+
+/* %ebx */
+#define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */
+#define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */
+#define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of Northbridge PMC */
+
+/*
* Centaur Extended Feature flags.
*/
#define CPUID_VIA_HAS_RNG 0x00000004 /* Random number generator */
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.130 src/usr.sbin/cpuctl/arch/i386.c:1.131
--- src/usr.sbin/cpuctl/arch/i386.c:1.130 Wed Nov 16 14:01:41 2022
+++ src/usr.sbin/cpuctl/arch/i386.c Wed Nov 16 14:55:50 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.130 2022/11/16 14:01:41 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.131 2022/11/16 14:55:50 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.130 2022/11/16 14:01:41 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.131 2022/11/16 14:55:50 msaitoh Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -2264,6 +2264,22 @@ identifycpu(int fd, const char *cpuname)
print_bits(cpuname, "Encrypted Memory features",
CPUID_AMD_ENCMEM_FLAGS, descs[0]);
}
+ if (ci->ci_max_ext_cpuid >= 0x80000022) {
+ uint8_t ncore, nnb, nlbrs;
+
+ x86_cpuid(0x80000022, descs);
+ print_bits(cpuname, "Perfmon:",
+ CPUID_AXPERF_FLAGS, descs[0]);
+
+ ncore = __SHIFTOUT(descs[1], CPUID_AXPERF_NCPC);
+ nnb = __SHIFTOUT(descs[1], CPUID_AXPERF_NNBPC);
+ nlbrs = __SHIFTOUT(descs[1], CPUID_AXPERF_NLBRSTACK);
+ aprint_verbose("%s: Perfmon: counters: "
+ "Core %hhu, Northbridge %hhu\n", cpuname,
+ ncore, nnb);
+ aprint_verbose("%s: Perfmon: LBR Stack %hhu entries\n",
+ cpuname, nlbrs);
+ }
} else if (cpu_vendor == CPUVENDOR_INTEL) {
if (ci->ci_max_cpuid >= 0x0a) {
unsigned int pmcver, ncounter, veclen;
