Module Name: src Committed By: skrll Date: Sat Dec 3 09:40:56 UTC 2022
Modified Files: src/sys/arch/riscv/sifive: files.sifive Log Message: Trailing whitespace To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/sifive/files.sifive Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/riscv/sifive/files.sifive diff -u src/sys/arch/riscv/sifive/files.sifive:1.1 src/sys/arch/riscv/sifive/files.sifive:1.2 --- src/sys/arch/riscv/sifive/files.sifive:1.1 Fri Nov 25 12:35:44 2022 +++ src/sys/arch/riscv/sifive/files.sifive Sat Dec 3 09:40:56 2022 @@ -1,10 +1,10 @@ -# $NetBSD: files.sifive,v 1.1 2022/11/25 12:35:44 jmcneill Exp $ +# $NetBSD: files.sifive,v 1.2 2022/12/03 09:40:56 skrll Exp $ # # Configuration info for SiFive SoCs # # # FU540 Power Reset Clocking Interrupt (PRCI) subsystem -device prci +device prci attach prci at fdt with fu540_prci file arch/riscv/sifive/fu540_prci.c fu540_prci