Module Name: src
Committed By: martin
Date: Wed Dec 28 14:38:07 UTC 2022
Modified Files:
src/sys/arch/evbmips/mipssim [netbsd-10]: machdep.c mipssim_dma.c
mipssimreg.h
Log Message:
Pull up following revision(s) (requested by he in ticket #26):
sys/arch/evbmips/mipssim/mipssim_dma.c: revision 1.2
sys/arch/evbmips/mipssim/mipssimreg.h: revision 1.4
sys/arch/evbmips/mipssim/machdep.c: revision 1.4
mipssim_dma.c: set _bounce_thresh so that bounce buffering works.
Suggested by jmcneill@, thanks!
evbmips/mipssim: on mips64, probe for additional memory.
Probe for memory from above the ISA I/O hole and up to 16GB,
which acording to simonb@ is a somewhat arbitrary limit.
This makes it possible to specify e.g. "-m 2g" to qemu, and have
that memory be probed instead of being clamped to 508MB.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.3.4.1 src/sys/arch/evbmips/mipssim/machdep.c
cvs rdiff -u -r1.1 -r1.1.20.1 src/sys/arch/evbmips/mipssim/mipssim_dma.c
cvs rdiff -u -r1.3 -r1.3.20.1 src/sys/arch/evbmips/mipssim/mipssimreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/evbmips/mipssim/machdep.c
diff -u src/sys/arch/evbmips/mipssim/machdep.c:1.3 src/sys/arch/evbmips/mipssim/machdep.c:1.3.4.1
--- src/sys/arch/evbmips/mipssim/machdep.c:1.3 Tue Nov 16 06:44:40 2021
+++ src/sys/arch/evbmips/mipssim/machdep.c Wed Dec 28 14:38:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.3 2021/11/16 06:44:40 simonb Exp $ */
+/* $NetBSD: machdep.c,v 1.3.4.1 2022/12/28 14:38:07 martin Exp $ */
/*-
* Copyright (c) 2001,2021 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3 2021/11/16 06:44:40 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.3.4.1 2022/12/28 14:38:07 martin Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -229,6 +229,9 @@ mach_init_memory(void)
size_t addr;
uint32_t *memptr;
extern char end[]; /* XXX */
+#ifdef MIPS64
+ size_t highaddr;
+#endif
l->l_addr = &dummypcb;
memsize = roundup2(MIPS_KSEG0_TO_PHYS((uintptr_t)(end)), 1024 * 1024);
@@ -246,13 +249,43 @@ mach_init_memory(void)
}
l->l_addr = NULL;
- printf("Memory size: 0x%" PRIxPSIZE " (%" PRIdPSIZE " MB)\n",
- memsize, memsize / 1024 / 1024);
physmem = btoc(memsize);
mem_clusters[0].start = PAGE_SIZE;
mem_clusters[0].size = memsize - PAGE_SIZE;
mem_cluster_cnt = 1;
+
+#ifdef _LP64
+ /* probe for more memory above ISA I/O "hole" */
+ l->l_addr = &dummypcb;
+
+ for (highaddr = addr = MIPSSIM_MORE_MEM_BASE;
+ addr < MIPSSIM_MORE_MEM_END;
+ addr += 1024 * 1024) {
+ memptr = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE,
+ addr - sizeof(*memptr));
+ if (badaddr(memptr, sizeof(uint32_t)) < 0)
+ break;
+
+ highaddr = addr;
+#ifdef MEM_DEBUG
+ printf("probed %zd MB\n", (addr - MIPSSIM_MORE_MEM_BASE)
+ / 1024 * 1024);
+#endif
+ }
+ l->l_addr = NULL;
+
+ if (highaddr != MIPSSIM_MORE_MEM_BASE) {
+ mem_clusters[1].start = MIPSSIM_MORE_MEM_BASE;
+ mem_clusters[1].size = highaddr - MIPSSIM_MORE_MEM_BASE;
+ mem_cluster_cnt++;
+ physmem += btoc(mem_clusters[1].size);
+ memsize += mem_clusters[1].size;
+ }
+#endif /* _LP64 */
+
+ printf("Memory size: 0x%" PRIxPSIZE " (%" PRIdPSIZE " MB)\n",
+ memsize, memsize / 1024 / 1024);
}
void
Index: src/sys/arch/evbmips/mipssim/mipssim_dma.c
diff -u src/sys/arch/evbmips/mipssim/mipssim_dma.c:1.1 src/sys/arch/evbmips/mipssim/mipssim_dma.c:1.1.20.1
--- src/sys/arch/evbmips/mipssim/mipssim_dma.c:1.1 Mon Feb 15 22:39:46 2021
+++ src/sys/arch/evbmips/mipssim/mipssim_dma.c Wed Dec 28 14:38:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: mipssim_dma.c,v 1.1 2021/02/15 22:39:46 reinoud Exp $ */
+/* $NetBSD: mipssim_dma.c,v 1.1.20.1 2022/12/28 14:38:07 martin Exp $ */
/*-
* Copyright (c) 2021 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mipssim_dma.c,v 1.1 2021/02/15 22:39:46 reinoud Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mipssim_dma.c,v 1.1.20.1 2022/12/28 14:38:07 martin Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -57,6 +57,7 @@ mipssim_dma_init(struct mipssim_config *
t->_wbase = MIPSSIM_DMA_BASE;
t->_bounce_alloc_lo = MIPSSIM_DMA_PHYSBASE;
t->_bounce_alloc_hi = MIPSSIM_DMA_PHYSBASE + MIPSSIM_DMA_SIZE;
+ t->_bounce_thresh = t->_bounce_alloc_hi; /* as an approximation */
t->_dmamap_ops = mips_bus_dmamap_ops;
t->_dmamem_ops = mips_bus_dmamem_ops;
t->_dmatag_ops = mips_bus_dmatag_ops;
Index: src/sys/arch/evbmips/mipssim/mipssimreg.h
diff -u src/sys/arch/evbmips/mipssim/mipssimreg.h:1.3 src/sys/arch/evbmips/mipssim/mipssimreg.h:1.3.20.1
--- src/sys/arch/evbmips/mipssim/mipssimreg.h:1.3 Tue Feb 16 15:06:30 2021
+++ src/sys/arch/evbmips/mipssim/mipssimreg.h Wed Dec 28 14:38:07 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: mipssimreg.h,v 1.3 2021/02/16 15:06:30 simonb Exp $ */
+/* $NetBSD: mipssimreg.h,v 1.3.20.1 2022/12/28 14:38:07 martin Exp $ */
/*-
* Copyright (c) 2021 The NetBSD Foundation, Inc.
@@ -37,6 +37,11 @@
* 1fd0.0000 64kB ISA IO space
* 1fd1.0000 64kB 'ISA' VirtIO IO space (non standard)
*
+ * Additionally, mips64 probes for memory up to 16G:
+ *
+ * 2000.0000 memory, probed, up to
+ * 4.0000.0000 16GB somewhat arbitrarily, could probably be higher
+ *
* CPU interrupts
*
* 0 mipsnet
@@ -56,5 +61,8 @@
#define MIPSSIM_DMA_PHYSBASE 0x00000000
#define MIPSSIM_DMA_SIZE (MIPSSIM_ISA_IO_BASE - MIPSSIM_DMA_BASE)
+#define MIPSSIM_MORE_MEM_BASE 0x20000000
+#define MIPSSIM_MORE_MEM_END (16ULL * 1024 * 1024 * 1024) /* 16GB */
+
#define VIRTIO_NUM_TRANSPORTS 32
#define VIRTIO_STRIDE 512
