Module Name: src
Committed By: msaitoh
Date: Fri Dec 30 14:50:52 UTC 2022
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Fix comment.
To generate a diff of this commit:
cvs rdiff -u -r1.200 -r1.201 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.200 src/sys/arch/x86/include/specialreg.h:1.201
--- src/sys/arch/x86/include/specialreg.h:1.200 Fri Dec 30 12:12:54 2022
+++ src/sys/arch/x86/include/specialreg.h Fri Dec 30 14:50:52 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.200 2022/12/30 12:12:54 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.201 2022/12/30 14:50:52 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -550,10 +550,10 @@
/* %ecx = 2, %edx */
#define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */
-#define CPUID_SEF_IPRED_CTRL __BIT(1) /* bit 3&4 */
-#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* bit 5 */
-#define CPUID_SEF_DDPD_U __BIT(3) /* bit 8 Data Dependent Prefetcher */
-#define CPUID_SEF_BHI_CTRL __BIT(4) /* bit 10 */
+#define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */
+#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */
+#define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */
+#define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */
#define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */
#define CPUID_SEF2_FLAGS_D "\20" \
