Module Name: src Committed By: msaitoh Date: Fri Dec 30 15:25:15 UTC 2022
Modified Files: src/sys/dev/pci: pcidevs.h pcidevs_data.h Log Message: Regen. To generate a diff of this commit: cvs rdiff -u -r1.1453 -r1.1454 src/sys/dev/pci/pcidevs.h cvs rdiff -u -r1.1452 -r1.1453 src/sys/dev/pci/pcidevs_data.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/dev/pci/pcidevs.h diff -u src/sys/dev/pci/pcidevs.h:1.1453 src/sys/dev/pci/pcidevs.h:1.1454 --- src/sys/dev/pci/pcidevs.h:1.1453 Wed Dec 28 13:27:11 2022 +++ src/sys/dev/pci/pcidevs.h Fri Dec 30 15:25:14 2022 @@ -1,10 +1,10 @@ -/* $NetBSD: pcidevs.h,v 1.1453 2022/12/28 13:27:11 msaitoh Exp $ */ +/* $NetBSD: pcidevs.h,v 1.1454 2022/12/30 15:25:14 msaitoh Exp $ */ /* * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * NetBSD: pcidevs,v 1.1472 2022/12/28 13:26:44 msaitoh Exp + * NetBSD: pcidevs,v 1.1473 2022/12/30 15:24:38 msaitoh Exp */ /* @@ -5919,6 +5919,7 @@ #define PCI_PRODUCT_INTEL_EHL_SIO_I2C_3 0x4b7b /* Elkhart Lake SIO I2C 3 */ #define PCI_PRODUCT_INTEL_EHL_XHCI 0x4b7d /* Elkhart Lake xHCI */ #define PCI_PRODUCT_INTEL_EHL_XDCI 0x4b7e /* Elkhart Lake xDCI */ +#define PCI_PRODUCT_INTEL_EHL_SSRAM 0x4b7f /* Elkhart Lake Shared SRAM */ #define PCI_PRODUCT_INTEL_EHL_PSE_QEP_1 0x4b81 /* Elkhart Lake PSE QEP 1 */ #define PCI_PRODUCT_INTEL_EHL_PSE_QEP_2 0x4b82 /* Elkhart Lake PSE QEP 2 */ #define PCI_PRODUCT_INTEL_EHL_PSE_QEP_3 0x4b83 /* Elkhart Lake PSE QEP 3 */ Index: src/sys/dev/pci/pcidevs_data.h diff -u src/sys/dev/pci/pcidevs_data.h:1.1452 src/sys/dev/pci/pcidevs_data.h:1.1453 --- src/sys/dev/pci/pcidevs_data.h:1.1452 Wed Dec 28 13:27:10 2022 +++ src/sys/dev/pci/pcidevs_data.h Fri Dec 30 15:25:14 2022 @@ -1,10 +1,10 @@ -/* $NetBSD: pcidevs_data.h,v 1.1452 2022/12/28 13:27:10 msaitoh Exp $ */ +/* $NetBSD: pcidevs_data.h,v 1.1453 2022/12/30 15:25:14 msaitoh Exp $ */ /* * THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * NetBSD: pcidevs,v 1.1472 2022/12/28 13:26:44 msaitoh Exp + * NetBSD: pcidevs,v 1.1473 2022/12/30 15:24:38 msaitoh Exp */ /* @@ -10539,6 +10539,8 @@ static const uint32_t pci_products[] = { 28757, 23042, 8183, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_XDCI, 28757, 23042, 23258, 0, + PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_SSRAM, + 28757, 23042, 23263, 23270, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE_QEP_1, 28757, 23042, 29240, 29244, 8079, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE_QEP_2, @@ -20858,7 +20860,7 @@ static const char pci_words[] = { "." "TwinTurbo\0" /* 1 refs @ 23022 */ "128M\0" /* 1 refs @ 23032 */ "Iron\0" /* 6 refs @ 23037 */ - "Lake\0" /* 408 refs @ 23042 */ + "Lake\0" /* 409 refs @ 23042 */ "Core\0" /* 181 refs @ 23047 */ "Centrino\0" /* 28 refs @ 23052 */ "Advanced-N\0" /* 10 refs @ 23061 */ @@ -20898,8 +20900,8 @@ static const char pci_words[] = { "." "2x1\0" /* 5 refs @ 23250 */ "1x1\0" /* 7 refs @ 23254 */ "xDCI\0" /* 8 refs @ 23258 */ - "Shared\0" /* 12 refs @ 23263 */ - "SRAM\0" /* 12 refs @ 23270 */ + "Shared\0" /* 13 refs @ 23263 */ + "SRAM\0" /* 13 refs @ 23270 */ "CNVi\0" /* 8 refs @ 23275 */ "SDXC\0" /* 5 refs @ 23280 */ "Thermal\0" /* 45 refs @ 23285 */ @@ -21698,7 +21700,7 @@ static const char pci_words[] = { "." "mobile)\0" /* 4 refs @ 28738 */ "(RAID,\0" /* 6 refs @ 28746 */ "2x2\0" /* 2 refs @ 28753 */ - "Elkhart\0" /* 119 refs @ 28757 */ + "Elkhart\0" /* 120 refs @ 28757 */ "(2C,\0" /* 1 refs @ 28765 */ "(SKU\0" /* 25 refs @ 28770 */ "8)\0" /* 1 refs @ 28775 */