Module Name: src Committed By: martin Date: Mon Jan 23 12:16:00 UTC 2023
Modified Files: src/share/man/man4 [netbsd-10]: igpio.4 src/sys/dev/ic [netbsd-10]: igpio.c igpioreg.h igpiovar.h Log Message: Pull up following revision(s) (requested by msaitoh in ticket #53): sys/dev/ic/igpio.c: revision 1.5 sys/dev/ic/igpioreg.h: revision 1.3 sys/dev/ic/igpioreg.h: revision 1.4 sys/dev/ic/igpioreg.h: revision 1.5 sys/dev/ic/igpioreg.h: revision 1.6 sys/dev/ic/igpioreg.h: revision 1.7 sys/dev/ic/igpioreg.h: revision 1.8 sys/dev/ic/igpiovar.h: revision 1.2 share/man/man4/igpio.4: revision 1.3 Fix entries for Lewisburg. One more fix for Lewisburg. Modify comment. Whitespace. No functional change. Whitespace. No functional change. Whitespace. No functional change. Move entries of Alder Lake-S and Tiger Lake-LP. No functional change. igpio: Update pin definitions. - Add Ice Lake-N(INT34C3) - Add Raptor Lake-S(INTC1085). - Add another Baytrail(INT33FC). - Modify INTC1057. It was for Tiger Lake-LP and reused for Alder Lake-N. - Fix pin group definitions for Sunrisepoint-LP, Tiger Lake-LP, Tiger Lake-H, Alder Lake-P and Lewisburg. - Modify pin group names for Coffee Lake-S, Sunrisepoint-H, Cannon Lake-LP and Denverton. - Add two missing entries to Ice Lake-LP's pin group table. - Modify comment. INT3455 is Ice Lake-LP. - Add comment. igpio.4: Update list of supported devices. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.2.2.1 src/share/man/man4/igpio.4 cvs rdiff -u -r1.4 -r1.4.4.1 src/sys/dev/ic/igpio.c cvs rdiff -u -r1.2 -r1.2.4.1 src/sys/dev/ic/igpioreg.h cvs rdiff -u -r1.1 -r1.1.4.1 src/sys/dev/ic/igpiovar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/share/man/man4/igpio.4 diff -u src/share/man/man4/igpio.4:1.2 src/share/man/man4/igpio.4:1.2.2.1 --- src/share/man/man4/igpio.4:1.2 Thu Mar 24 16:33:58 2022 +++ src/share/man/man4/igpio.4 Mon Jan 23 12:16:00 2023 @@ -1,4 +1,4 @@ -.\" $NetBSD: igpio.4,v 1.2 2022/03/24 16:33:58 wiz Exp $ +.\" $NetBSD: igpio.4,v 1.2.2.1 2023/01/23 12:16:00 martin Exp $ .\" .\" Copyright (c) 2022 The NetBSD Foundation, Inc. .\" All rights reserved. @@ -27,7 +27,7 @@ .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE .\" POSSIBILITY OF SUCH DAMAGE. .\" -.Dd March 24, 2022 +.Dd January 7, 2023 .Dt IGPIO 4 .Os .Sh NAME @@ -42,23 +42,28 @@ provides a .Xr gpio 4 interface for the following Intel chipsets: .Bl -tag -width autoselect -compact -.It Alderlake +.It Alder Lake-N +.It Alder Lake-P +.It Alder Lake-S .It Baytrail -.It Cannonlake-H -.It Cannonlake-LP +.It Cannon Lake-H +.It Cannon Lake-LP .It Cedarfork +.It Coffee Lake-S .It Denverton .It Emmitsburg -.It Geminilake -.It Icelake -.It Jasperlake +.It Gemini Lake +.It Ice Lake-LP +.It Ice Lake-N +.It Jasper Lake .It Lakefield .It Lewisburg .It Lynxpoint +.It Raptor Lake-S .It Sunrisepoint-H .It Sunrisepoint-LP -.It Tigerlake-H -.It Tigerlake-LP +.It Tiger Lake-H +.It Tiger Lake-LP .El Support for Broxton and Cherryview is not enabled yet. .Pp Index: src/sys/dev/ic/igpio.c diff -u src/sys/dev/ic/igpio.c:1.4 src/sys/dev/ic/igpio.c:1.4.4.1 --- src/sys/dev/ic/igpio.c:1.4 Sat Mar 26 19:35:56 2022 +++ src/sys/dev/ic/igpio.c Mon Jan 23 12:15:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: igpio.c,v 1.4 2022/03/26 19:35:56 riastradh Exp $ */ +/* $NetBSD: igpio.c,v 1.4.4.1 2023/01/23 12:15:59 martin Exp $ */ /* * Copyright (c) 2021,2022 Emmanuel Dreyfus @@ -301,7 +301,7 @@ igpio_attach(struct igpio_softc *sc) DPRINTF(("padbar[%d] = #%x\n", i, ib->ib_padbar)); if (ib->ib_padbar > sc->sc_length[i]) { printf("PADBAR = #%x higher than max #%lx\n", - ib->ib_padbar, sc->sc_length[i]); + ib->ib_padbar, sc->sc_length[i]); goto out; } @@ -320,7 +320,7 @@ igpio_attach(struct igpio_softc *sc) npins = 1 + ibs->ibs_last_pin - ibs->ibs_first_pin; ib->ib_intr = - kmem_zalloc(sizeof(*ib->ib_intr) * npins, KM_SLEEP); + kmem_zalloc(sizeof(*ib->ib_intr) * npins, KM_SLEEP); sc->sc_npins += npins; } @@ -640,8 +640,8 @@ igpio_intr_establish(void *priv, int pin newval |= IGPIO_PADCFG0_RXEVCFG_EDGE_BOTH; break; case GPIO_INTR_NEG_EDGE: - newval |= IGPIO_PADCFG0_RXEVCFG_EDGE; - newval |= IGPIO_PADCFG0_RXINV; + newval |= IGPIO_PADCFG0_RXEVCFG_EDGE; + newval |= IGPIO_PADCFG0_RXINV; break; case GPIO_INTR_POS_EDGE: newval |= IGPIO_PADCFG0_RXEVCFG_EDGE; Index: src/sys/dev/ic/igpioreg.h diff -u src/sys/dev/ic/igpioreg.h:1.2 src/sys/dev/ic/igpioreg.h:1.2.4.1 --- src/sys/dev/ic/igpioreg.h:1.2 Sat Mar 26 19:35:35 2022 +++ src/sys/dev/ic/igpioreg.h Mon Jan 23 12:15:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: igpioreg.h,v 1.2 2022/03/26 19:35:35 riastradh Exp $ */ +/* $NetBSD: igpioreg.h,v 1.2.4.1 2023/01/23 12:15:59 martin Exp $ */ /* * Copyright (c) 2021 Emmanuel Dreyfus @@ -82,8 +82,8 @@ struct igpio_bank_setup { int ibs_barno; int ibs_first_pin; int ibs_last_pin; - int ibs_gpi_is; - int ibs_gpi_ie; + int ibs_gpi_is; /* Interrupt Status */ + int ibs_gpi_ie; /* Interrupt Enable */ }; struct igpio_pin_group { @@ -99,7 +99,7 @@ struct igpio_bank_setup igpio_bank_setup { "INT344B", 1, 48, 119, 0x100, 0x120 }, { "INT344B", 2, 120, 151, 0x100, 0x120 }, - /* Sunrisepoint-H */ + /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */ { "INT3451", 0, 0, 47, 0x100, 0x120 }, { "INT3451", 1, 48, 180, 0x100, 0x120 }, { "INT3451", 2, 181, 191, 0x100, 0x120 }, @@ -117,91 +117,104 @@ struct igpio_bank_setup igpio_bank_setup { "INT33C7", 0, 0, 94, 0x000, 0x000 }, { "INT3437", 0, 0, 94, 0x000, 0x000 }, - /* Cannonlake-H */ + /* Cannon Lake-H */ { "INT3450", 0, 0, 50, 0x100, 0x120 }, { "INT3450", 1, 51, 154, 0x100, 0x120 }, { "INT3450", 2, 155, 248, 0x100, 0x120 }, { "INT3450", 3, 249, 298, 0x100, 0x120 }, - /* Cannonlake-LP */ + /* Cannon Lake-LP */ { "INT34BB", 0, 0, 67, 0x100, 0x120 }, { "INT34BB", 1, 68, 180, 0x100, 0x120 }, { "INT34BB", 2, 181, 243, 0x100, 0x120 }, - /* Alderlake */ - { "INTC1056", 0, 0, 94, 0x200, 0x220 }, - { "INTC1056", 1, 95, 150, 0x200, 0x220 }, - { "INTC1056", 2, 151, 199, 0x200, 0x220 }, - { "INTC1056", 3, 200, 269, 0x200, 0x220 }, - { "INTC1056", 4, 270, 303, 0x200, 0x220 }, - - /* Icelake */ + /* Ice Lake-LP */ { "INT3455", 0, 0, 58, 0x100, 0x110 }, { "INT3455", 1, 59, 152, 0x100, 0x110 }, { "INT3455", 2, 153, 215, 0x100, 0x110 }, { "INT3455", 3, 216, 240, 0x100, 0x110 }, + /* Ice Lake-N */ + { "INT34C3", 0, 0, 71, 0x100, 0x120 }, + { "INT34C3", 1, 72, 174, 0x100, 0x120 }, + { "INT34C3", 2, 175, 204, 0x100, 0x120 }, + { "INT34C3", 3, 205, 212, 0x100, 0x120 }, + /* Lakefield */ { "INT34C4", 0, 0, 59, 0x100, 0x110 }, { "INT34C4", 1, 60, 148, 0x100, 0x110 }, { "INT34C4", 2, 149, 237, 0x100, 0x110 }, { "INT34C4", 3, 238, 266, 0x100, 0x110 }, - /* Tigerlake-LP */ + /* Tiger Lake-LP */ { "INT34C5", 0, 0, 66, 0x100, 0x120 }, { "INT34C5", 1, 67, 170, 0x100, 0x120 }, { "INT34C5", 2, 171, 259, 0x100, 0x120 }, { "INT34C5", 3, 260, 276, 0x100, 0x120 }, - /* Tigerlake-LP */ - { "INTC1055", 0, 0, 66, 0x100, 0x120 }, - { "INTC1055", 1, 67, 170, 0x100, 0x120 }, - { "INTC1055", 2, 171, 259, 0x100, 0x120 }, - { "INTC1055", 3, 260, 276, 0x100, 0x120 }, - - /* Tigerlake-LP */ - { "INTC1057", 0, 0, 66, 0x100, 0x120 }, - { "INTC1057", 1, 67, 170, 0x100, 0x120 }, - { "INTC1057", 2, 171, 259, 0x100, 0x120 }, - { "INTC1057", 3, 260, 276, 0x100, 0x120 }, + /* Alder Lake-P (Same as Tiger Lake-LP(INT34C5)) */ + { "INTC1055", 0, 0, 66, 0x100, 0x120 }, + { "INTC1055", 1, 67, 170, 0x100, 0x120 }, + { "INTC1055", 2, 171, 259, 0x100, 0x120 }, + { "INTC1055", 3, 260, 276, 0x100, 0x120 }, - /* Tigerlake-H */ + /* Tiger Lake-H */ { "INT34C6", 0, 0, 78, 0x100, 0x120 }, { "INT34C6", 1, 79, 180, 0x100, 0x120 }, { "INT34C6", 2, 181, 217, 0x100, 0x120 }, { "INT34C6", 3, 218, 266, 0x100, 0x120 }, { "INT34C6", 4, 267, 290, 0x100, 0x120 }, - /* Jasperlake */ + /* Jasper Lake */ { "INT34C8", 0, 0, 91, 0x100, 0x120 }, { "INT34C8", 1, 92, 194, 0x100, 0x120 }, { "INT34C8", 2, 195, 224, 0x100, 0x120 }, { "INT34C8", 3, 225, 232, 0x100, 0x120 }, + /* Alder Lake-S */ + { "INTC1056", 0, 0, 94, 0x200, 0x220 }, + { "INTC1056", 1, 95, 150, 0x200, 0x220 }, + { "INTC1056", 2, 151, 199, 0x200, 0x220 }, + { "INTC1056", 3, 200, 269, 0x200, 0x220 }, + { "INTC1056", 4, 270, 303, 0x200, 0x220 }, + + /* Alder Lake-N */ + { "INTC1057", 0, 0, 66, 0x100, 0x120 }, + { "INTC1057", 1, 67, 168, 0x100, 0x120 }, + { "INTC1057", 2, 169, 248, 0x100, 0x120 }, + { "INTC1057", 3, 249, 256, 0x100, 0x120 }, + + /* Raptor Lake-S (Same as Alder Lake-S(INTC1056)) */ + { "INTC1085", 0, 0, 94, 0x200, 0x220 }, + { "INTC1085", 1, 95, 150, 0x200, 0x220 }, + { "INTC1085", 2, 151, 199, 0x200, 0x220 }, + { "INTC1085", 3, 200, 269, 0x200, 0x220 }, + { "INTC1085", 4, 270, 303, 0x200, 0x220 }, + /* Lewisburg */ - { "INT3536", 0, 0, 7, 0x100, 0x110 }, - { "INT3536", 1, 72, 13, 0x100, 0x110 }, - { "INT3536", 3, 133, 14, 0x100, 0x110 }, - { "INT3536", 4, 144, 17, 0x100, 0x110 }, + { "INT3536", 0, 0, 71, 0x100, 0x110 }, + { "INT3536", 1, 72, 132, 0x100, 0x110 }, + { "INT3536", 3, 133, 143, 0x100, 0x110 }, + { "INT3536", 4, 144, 178, 0x100, 0x110 }, { "INT3536", 5, 179, 246, 0x100, 0x110 }, /* Emmitsburg */ - { "INTC1071", 0, 0, 65, 0x200, 0x210 }, - { "INTC1071", 1, 66, 111, 0x200, 0x210 }, - { "INTC1071", 2, 112, 145, 0x200, 0x210 }, - { "INTC1071", 3, 146, 183, 0x200, 0x210 }, - { "INTC1071", 4, 184, 261, 0x200, 0x210 }, + { "INTC1071", 0, 0, 65, 0x200, 0x210 }, + { "INTC1071", 1, 66, 111, 0x200, 0x210 }, + { "INTC1071", 2, 112, 145, 0x200, 0x210 }, + { "INTC1071", 3, 146, 183, 0x200, 0x210 }, + { "INTC1071", 4, 184, 261, 0x200, 0x210 }, /* Denverton */ - { "INTC3000", 0, 0, 40, 0x100, 0x120 }, - { "INTC3000", 1, 41, 153, 0x100, 0x120 }, + { "INTC3000", 0, 0, 40, 0x100, 0x120 }, + { "INTC3000", 1, 41, 153, 0x100, 0x120 }, /* Cedarfork */ - { "INTC3001", 0, 0, 167, 0x200, 0x230 }, - { "INTC3001", 1, 168, 236, 0x200, 0x230 }, + { "INTC3001", 0, 0, 167, 0x200, 0x230 }, + { "INTC3001", 1, 168, 236, 0x200, 0x230 }, - /* Geminilake */ - { "INT3453", 0, 0, 34, 0x100, 0x110 }, + /* Gemini Lake */ + { "INT3453", 0, 0, 34, 0x100, 0x110 }, #ifdef notyet /* @@ -210,267 +223,297 @@ struct igpio_bank_setup igpio_bank_setup /* Broxton */ { "apollolake-pinctrl", 0, 0, 0, 0x100, 0x110 }, { "broxton-pinctrl", 0, 0, 0, 0x100, 0x110 }, - { "INT34D1", 0, 0, 0, 0x100, 0x110 }, - { "INT3452", 0, 0, 0, 0x100, 0x110 }, + { "INT34D1", 0, 0, 0, 0x100, 0x110 }, + { "INT3452", 0, 0, 0, 0x100, 0x110 }, /* Cherryview */ - { "INT33FF", 0, 0, 0, 0x000, 0x000 }, + { "INT33FF", 0, 0, 0, 0x000, 0x000 }, #endif - { NULL, 0, 0, 0, 0x000, 0x000 }, + { NULL, 0, 0, 0, 0x000, 0x000 }, }; struct igpio_pin_group igpio_pin_group[] = { /* Sunrisepoint-LP */ - { "INT344B", 0, 151, "A" }, + { "INT344B", 0, 0, "GPP_A" }, + { "INT344B", 1, 24, "GPP_B" }, + { "INT344B", 0, 48, "GPP_C" }, + { "INT344B", 1, 72, "GPP_D" }, + { "INT344B", 2, 96, "GPP_E" }, + { "INT344B", 0, 120, "GPP_F" }, + + /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */ + { "INT3451", 0, 0, "GPP_A" }, + { "INT3451", 1, 24, "GPP_B" }, + { "INT3451", 0, 48, "GPP_C" }, + { "INT3451", 1, 72, "GPP_D" }, + { "INT3451", 2, 96, "GPP_E" }, + { "INT3451", 3, 109, "GPP_F" }, + { "INT3451", 4, 133, "GPP_G" }, + { "INT3451", 5, 157, "GPP_H" }, + { "INT3451", 0, 181, "GPP_I" }, /* Sunrisepoint-H */ - { "INT3451", 0, 0, "A" }, - { "INT3451", 1, 24, "B" }, - { "INT3451", 0, 48, "C" }, - { "INT3451", 1, 72, "D" }, - { "INT3451", 2, 96, "E" }, - { "INT3451", 3, 109, "F" }, - { "INT3451", 4, 133, "G" }, - { "INT3451", 5, 157, "H" }, - { "INT3451", 0, 181, "I" }, - - /* Sunrisepoint-H */ - { "INT345D", 0, 0, "A" }, - { "INT345D", 1, 24, "B" }, - { "INT345D", 0, 48, "C" }, - { "INT345D", 1, 72, "D" }, - { "INT345D", 2, 96, "E" }, - { "INT345D", 3, 109, "F" }, - { "INT345D", 4, 133, "G" }, - { "INT345D", 5, 157, "H" }, - { "INT345D", 0, 181, "I" }, + { "INT345D", 0, 0, "GPP_A" }, + { "INT345D", 1, 24, "GPP_B" }, + { "INT345D", 0, 48, "GPP_C" }, + { "INT345D", 1, 72, "GPP_D" }, + { "INT345D", 2, 96, "GPP_E" }, + { "INT345D", 3, 109, "GPP_F" }, + { "INT345D", 4, 133, "GPP_G" }, + { "INT345D", 5, 157, "GPP_H" }, + { "INT345D", 0, 181, "GPP_I" }, /* Baytrail */ - { "INT33B2", 0, 101, "A" }, + { "INT33B2", 0, 101, "A" }, + { "INT33FC", 0, 101, "A" }, /* Lynxpoint */ - { "INT33C7", 0, 94, "A" }, - { "INT3437", 0, 94, "A" }, + { "INT33C7", 0, 94, "A" }, + { "INT3437", 0, 94, "A" }, + + /* Cannon Lake-H */ + { "INT3450", 0, 0, "GPP_A" }, + { "INT3450", 1, 25, "GPP_B" }, + { "INT3450", 0, 51, "GPP_C" }, + { "INT3450", 1, 75, "GPP_D" }, + { "INT3450", 2, 99, "GPP_G" }, + { "INT3450", 3, 107, "AZA" }, + { "INT3450", 4, 115, "vGPIO_0" }, + { "INT3450", 5, 147, "vGPIO_1" }, + { "INT3450", 0, 155, "GPP_K" }, + { "INT3450", 1, 179, "GPP_H" }, + { "INT3450", 2, 203, "GPP_E" }, + { "INT3450", 3, 216, "GPP_F" }, + { "INT3450", 4, 240, "SPI" }, + { "INT3450", 0, 249, "CPU" }, + { "INT3450", 1, 260, "JTAG" }, + { "INT3450", 2, 269, "GPP_I" }, + { "INT3450", 3, 287, "GPP_J" }, + + /* Cannon Lake-LP */ + { "INT34BB", 0, 0, "GPP_A" }, + { "INT34BB", 1, 25, "GPP_B" }, + { "INT34BB", 2, 51, "GPP_G" }, + { "INT34BB", 3, 59, "SPI" }, + { "INT34BB", 0, 68, "GPP_D" }, + { "INT34BB", 1, 93, "GPP_F" }, + { "INT34BB", 2, 117, "GPP_H" }, + { "INT34BB", 3, 141, "vGPIO_0" }, + { "INT34BB", 4, 173, "vGPIO_1" }, + { "INT34BB", 0, 181, "GPP_C" }, + { "INT34BB", 1, 205, "GPP_E" }, + { "INT34BB", 2, 229, "JTAG" }, + { "INT34BB", 3, 238, "HVCMOS" }, + + /* Ice Lake-LP */ + { "INT3455", 0, 0, "GPP_G" }, + { "INT3455", 1, 8, "GPP_B" }, + { "INT3455", 2, 34, "GPP_A" }, + { "INT3455", 0, 59, "GPP_H" }, + { "INT3455", 1, 83, "GPP_D" }, + { "INT3455", 2, 104, "GPP_F" }, + { "INT3455", 3, 124, "vGPIO" }, + { "INT3455", 0, 153, "GPP_C" }, + { "INT3455", 1, 177, "HVCMOS" }, + { "INT3455", 2, 183, "GPP_E" }, + { "INT3455", 3, 207, "JTAG" }, + { "INT3455", 0, 216, "GPP_R" }, + { "INT3455", 1, 224, "GPP_S" }, + { "INT3455", 2, 232, "SPI" }, + + /* Ice Lake-N */ + { "INT34C3", 0, 0, "SPI" }, + { "INT34C3", 1, 9, "GPP_B" }, + { "INT34C3", 2, 35, "GPP_A" }, + { "INT34C3", 3, 56, "GPP_S" }, + { "INT34C3", 4, 64, "GPP_R" }, + { "INT34C3", 0, 72, "GPP_H" }, + { "INT34C3", 1, 96, "GPP_D" }, + { "INT34C3", 2, 122, "vGPIO" }, + { "INT34C3", 3, 151, "GPP_C" }, + { "INT34C3", 0, 175, "HVCMOS" }, + { "INT34C3", 1, 181, "GPP_E" }, + { "INT34C3", 0, 205, "GPP_G" }, - /* Cannonlake-H */ - { "INT3450", 0, 0, "GPP_A" }, - { "INT3450", 1, 25, "GPP_B" }, - { "INT3450", 0, 51, "GPP_C" }, - { "INT3450", 1, 75, "GPP_D" }, - { "INT3450", 2, 99, "GPP_G" }, - { "INT3450", 3, 107, "AZA" }, - { "INT3450", 4, 115, "vGPIO_0" }, - { "INT3450", 5, 147, "vGPIO_1" }, - { "INT3450", 0, 155, "GPP_K" }, - { "INT3450", 1, 179, "GPP_H" }, - { "INT3450", 2, 203, "GPP_E" }, - { "INT3450", 3, 216, "GPP_F" }, - { "INT3450", 4, 240, "SPI" }, - { "INT3450", 0, 249, "CPU" }, - { "INT3450", 1, 260, "JTAG" }, - { "INT3450", 2, 269, "GPP_I" }, - { "INT3450", 3, 287, "GPP_J" }, - - /* Cannonlake-LP */ - { "INT34BB", 0, 0, "GPP_A" }, - { "INT34BB", 1, 25, "GPP_B" }, - { "INT34BB", 2, 51, "GPP_G" }, - { "INT34BB", 3, 59, "SPI" }, - { "INT34BB", 0, 68, "GPP_D" }, - { "INT34BB", 1, 93, "GPP_F" }, - { "INT34BB", 2, 117, "GPP_H" }, - { "INT34BB", 3, 141, "vGPIO" }, - { "INT34BB", 4, 173, "vGPIO" }, - { "INT34BB", 0, 181, "GPP_C" }, - { "INT34BB", 1, 205, "GPP_E" }, - { "INT34BB", 2, 229, "JTAG" }, - { "INT34BB", 3, 238, "HVCMOS" }, + /* Lakefield */ + { "INT34C4", 0, 0, "EAST_0" }, + { "INT34C4", 1, 32, "EAST_1" }, + { "INT34C4", 0, 60, "NORTHWEST_0" }, + { "INT34C4", 1, 92, "NORTHWEST_1" }, + { "INT34C4", 2, 124, "NORTHWEST_2" }, + { "INT34C4", 0, 149, "WEST_0" }, + { "INT34C4", 1, 181, "WEST_1" }, + { "INT34C4", 2, 213, "WEST_2" }, + { "INT34C4", 0, 238, "SOUTHEAST" }, + + /* Tiger Lake-LP */ + { "INT34C5", 0, 0, "GPP_B" }, + { "INT34C5", 1, 26, "GPP_T" }, + { "INT34C5", 2, 42, "GPP_A" }, + { "INT34C5", 0, 67, "GPP_S" }, + { "INT34C5", 1, 75, "GPP_H" }, + { "INT34C5", 2, 99, "GPP_D" }, + { "INT34C5", 3, 120, "GPP_U" }, + { "INT34C5", 4, 144, "vGPIO" }, + { "INT34C5", 0, 171, "GPP_C" }, + { "INT34C5", 1, 195, "GPP_F" }, + { "INT34C5", 2, 220, "HVCMOS" }, + { "INT34C5", 3, 226, "GPP_E" }, + { "INT34C5", 4, 251, "JTAG" }, + { "INT34C5", 0, 260, "GPP_R" }, + { "INT34C5", 1, 268, "SPI" }, + + /* Alder Lake-P (Same as Tiger Lake-LP(INT34C5)) */ + { "INTC1055", 0, 0, "GPP_B" }, + { "INTC1055", 1, 26, "GPP_T" }, + { "INTC1055", 2, 42, "GPP_A" }, + { "INTC1055", 0, 67, "GPP_S" }, + { "INTC1055", 1, 75, "GPP_H" }, + { "INTC1055", 2, 99, "GPP_D" }, + { "INTC1055", 3, 120, "GPP_U" }, + { "INTC1055", 4, 144, "vGPIO" }, + { "INTC1055", 0, 171, "GPP_C" }, + { "INTC1055", 1, 195, "GPP_F" }, + { "INTC1055", 2, 220, "HVCMOS" }, + { "INTC1055", 3, 226, "GPP_E" }, + { "INTC1055", 4, 251, "JTAG" }, + { "INTC1055", 0, 260, "GPP_R" }, + { "INTC1055", 1, 268, "SPI" }, + + /* Tiger Lake-H */ + { "INT34C6", 0, 0, "GPP_A" }, + { "INT34C6", 1, 25, "GPP_R" }, + { "INT34C6", 2, 45, "GPP_B" }, + { "INT34C6", 3, 71, "vGPIO_0" }, + { "INT34C6", 0, 79, "GPP_D" }, + { "INT34C6", 1, 105, "GPP_C" }, + { "INT34C6", 2, 129, "GPP_S" }, + { "INT34C6", 3, 137, "GPP_G" }, + { "INT34C6", 4, 154, "vGPIO" }, + { "INT34C6", 0, 181, "GPP_E" }, + { "INT34C6", 1, 194, "GPP_F" }, + { "INT34C6", 0, 218, "GPP_H" }, + { "INT34C6", 1, 242, "GPP_J" }, + { "INT34C6", 2, 252, "GPP_K" }, + { "INT34C6", 0, 267, "GPP_I" }, + { "INT34C6", 1, 282, "JTAG" }, + + /* Jasper Lake */ + { "INT34C8", 0, 0, "GPP_F" }, + { "INT34C8", 1, 20, "SPI" }, + { "INT34C8", 2, 29, "GPP_B" }, + { "INT34C8", 3, 55, "GPP_A" }, + { "INT34C8", 4, 76, "GPP_S" }, + { "INT34C8", 5, 84, "GPP_R" }, + { "INT34C8", 0, 92, "GPP_H" }, + { "INT34C8", 1, 116, "GPP_D" }, + { "INT34C8", 2, 142, "vGPIO" }, + { "INT34C8", 3, 171, "GPP_C" }, + { "INT34C8", 0, 195, "HVCMOS" }, + { "INT34C8", 1, 201, "GPP_E" }, + { "INT34C8", 0, 225, "GPP_G" }, - /* Alderlake */ - { "INTC1056", 0, 0, "GPP_I" }, + /* Alder Lake-S */ + { "INTC1056", 0, 0, "GPP_I" }, { "INTC1056", 1, 25, "GPP_R" }, { "INTC1056", 2, 48, "GPP_J" }, { "INTC1056", 3, 60, "vGPIO" }, { "INTC1056", 4, 87, "vGPIO_0" }, { "INTC1056", 0, 95, "GPP_B" }, - { "INTC1056", 1, 119, "GPP_G" }, - { "INTC1056", 2, 127, "GPP_H" }, - { "INTC1056", 0, 151, "SPI0" }, - { "INTC1056", 1, 160, "GPP_A" }, - { "INTC1056", 2, 176, "GPP_C" }, - { "INTC1056", 0, 200, "GPP_S" }, - { "INTC1056", 1, 208, "GPP_E" }, - { "INTC1056", 2, 231, "GPP_K" }, - { "INTC1056", 3, 246, "GPP_F" }, - { "INTC1056", 0, 270, "GPP_D" }, - { "INTC1056", 1, 295, "JTAG" }, - - - /* Icelake */ - { "INT3455", 0, 0, "GPP_G" }, - { "INT3455", 1, 8, "GPP_B" }, - { "INT3455", 2, 34, "GPP_A" }, - { "INT3455", 0, 59, "GPP_H" }, - { "INT3455", 1, 83, "GPP_D" }, - { "INT3455", 2, 104, "GPP_F" }, - { "INT3455", 3, 124, "vGPIO" }, - { "INT3455", 0, 153, "GPP_C" }, - { "INT3455", 1, 177, "HVCMOS" }, - { "INT3455", 2, 183, "GPP_E" }, - { "INT3455", 3, 207, "JTAG" }, - { "INT3455", 2, 232, "SPI" }, - - - /* Lakefield */ - { "INT34C4", 0, 0, "EAST_0" }, - { "INT34C4", 1, 32, "EAST_1" }, - { "INT34C4", 0, 60, "NORTHWEST_0" }, - { "INT34C4", 1, 92, "NORTHWEST_1" }, - { "INT34C4", 2, 124, "NORTHWEST_2" }, - { "INT34C4", 0, 149, "WEST_0" }, - { "INT34C4", 1, 181, "WEST_1" }, - { "INT34C4", 2, 213, "WEST_2" }, - { "INT34C4", 0, 238, "SOUTHEAST" }, - - - /* Tigerlake-LP */ - { "INT34C5", 0, 0, "GPP_A" }, - { "INT34C5", 1, 25, "GPP_R" }, - { "INT34C5", 2, 45, "GPP_B" }, - { "INT34C5", 3, 71, "vGPIO_0" }, - { "INT34C5", 0, 79, "GPP_D" }, - { "INT34C5", 1, 105, "GPP_C" }, - { "INT34C5", 2, 129, "GPP_S" }, - { "INT34C5", 3, 137, "GPP_G" }, - { "INT34C5", 4, 154, "vGPIO" }, - { "INT34C5", 0, 181, "GPP_E" }, - { "INT34C5", 1, 194, "GPP_F" }, - { "INT34C5", 0, 218, "GPP_H" }, - { "INT34C5", 1, 242, "GPP_J" }, - { "INT34C5", 2, 252, "GPP_K" }, - { "INT34C5", 0, 267, "GPP_I" }, - { "INT34C5", 1, 282, "JTAG" }, - - - /* Tigerlake-LP */ - { "INTC1055", 0, 0, "GPP_A" }, - { "INTC1055", 1, 25, "GPP_R" }, - { "INTC1055", 2, 45, "GPP_B" }, - { "INTC1055", 3, 71, "vGPIO_0" }, - { "INTC1055", 0, 79, "GPP_D" }, - { "INTC1055", 1, 105, "GPP_C" }, - { "INTC1055", 2, 129, "GPP_S" }, - { "INTC1055", 3, 137, "GPP_G" }, - { "INTC1055", 4, 154, "vGPIO" }, - { "INTC1055", 0, 181, "GPP_E" }, - { "INTC1055", 1, 194, "GPP_F" }, - { "INTC1055", 0, 218, "GPP_H" }, - { "INTC1055", 1, 242, "GPP_J" }, - { "INTC1055", 2, 252, "GPP_K" }, - { "INTC1055", 0, 267, "GPP_I" }, - { "INTC1055", 1, 282, "JTAG" }, - - - /* Tigerlake-LP */ - { "INTC1057", 0, 0, "GPP_A" }, - { "INTC1057", 1, 25, "GPP_R" }, - { "INTC1057", 2, 45, "GPP_B" }, - { "INTC1057", 3, 71, "vGPIO_0" }, - { "INTC1057", 0, 79, "GPP_D" }, - { "INTC1057", 1, 105, "GPP_C" }, - { "INTC1057", 2, 129, "GPP_S" }, - { "INTC1057", 3, 137, "GPP_G" }, - { "INTC1057", 4, 154, "vGPIO" }, - { "INTC1057", 0, 181, "GPP_E" }, - { "INTC1057", 1, 194, "GPP_F" }, - { "INTC1057", 0, 218, "GPP_H" }, - { "INTC1057", 1, 242, "GPP_J" }, - { "INTC1057", 2, 252, "GPP_K" }, - { "INTC1057", 0, 267, "GPP_I" }, - { "INTC1057", 1, 282, "JTAG" }, - - /* Tigerlake-H */ - { "INT34C6", 0, 0, "GPP_B" }, - { "INT34C6", 1, 26, "GPP_T" }, - { "INT34C6", 2, 42, "GPP_A" }, - { "INT34C6", 0, 67, "GPP_S" }, - { "INT34C6", 1, 75, "GPP_H" }, - { "INT34C6", 2, 99, "GPP_D" }, - { "INT34C6", 3, 120, "GPP_U" }, - { "INT34C6", 4, 144, "vGPIO" }, - { "INT34C6", 0, 171, "GPP_C" }, - { "INT34C6", 1, 195, "GPP_F" }, - { "INT34C6", 2, 220, "HVCMOS" }, - { "INT34C6", 3, 226, "GPP_E" }, - { "INT34C6", 4, 251, "JTAG" }, - { "INT34C6", 0, 260, "GPP_R" }, - { "INT34C6", 1, 268, "SPI" }, - - /* Jasperlake */ - { "INT34C8", 0, 0, "GPP_F" }, - { "INT34C8", 1, 20, "SPI" }, - { "INT34C8", 2, 29, "GPP_B" }, - { "INT34C8", 3, 55, "GPP_A" }, - { "INT34C8", 4, 76, "GPP_S" }, - { "INT34C8", 5, 84, "GPP_R" }, - { "INT34C8", 0, 92, "GPP_H" }, - { "INT34C8", 1, 116, "GPP_D" }, - { "INT34C8", 2, 142, "vGPIO" }, - { "INT34C8", 3, 171, "GPP_C" }, - { "INT34C8", 0, 195, "HVCMOS" }, - { "INT34C8", 1, 201, "GPP_E" }, - { "INT34C8", 0, 225, "GPP_G" }, - + { "INTC1056", 1, 119, "GPP_G" }, + { "INTC1056", 2, 127, "GPP_H" }, + { "INTC1056", 0, 151, "SPI0" }, + { "INTC1056", 1, 160, "GPP_A" }, + { "INTC1056", 2, 176, "GPP_C" }, + { "INTC1056", 0, 200, "GPP_S" }, + { "INTC1056", 1, 208, "GPP_E" }, + { "INTC1056", 2, 231, "GPP_K" }, + { "INTC1056", 3, 246, "GPP_F" }, + { "INTC1056", 0, 270, "GPP_D" }, + { "INTC1056", 1, 295, "JTAG" }, + + /* Alder Lake-N */ + { "INTC1057", 0, 0, "GPP_B" }, + { "INTC1057", 1, 26, "GPP_T" }, + { "INTC1057", 2, 42, "GPP_A" }, + { "INTC1057", 0, 67, "GPP_S" }, + { "INTC1057", 1, 75, "GPP_I" }, + { "INTC1057", 2, 95, "GPP_H" }, + { "INTC1057", 3, 119, "GPP_D" }, + { "INTC1057", 4, 140, "vGPIO" }, + { "INTC1057", 0, 169, "GPP_C" }, + { "INTC1057", 1, 193, "GPP_F" }, + { "INTC1057", 2, 218, "HVCMOS" }, + { "INTC1057", 3, 224, "GPP_E" }, + { "INTC1057", 0, 249, "GPP_R" }, + + /* Raptor Lake-S (Same as Alder Lake-S(INTC1056)) */ + { "INTC1085", 0, 0, "GPP_I" }, + { "INTC1085", 1, 25, "GPP_R" }, + { "INTC1085", 2, 48, "GPP_J" }, + { "INTC1085", 3, 60, "vGPIO" }, + { "INTC1085", 4, 87, "vGPIO_0" }, + { "INTC1085", 0, 95, "GPP_B" }, + { "INTC1085", 1, 119, "GPP_G" }, + { "INTC1085", 2, 127, "GPP_H" }, + { "INTC1085", 0, 151, "SPI0" }, + { "INTC1085", 1, 160, "GPP_A" }, + { "INTC1085", 2, 176, "GPP_C" }, + { "INTC1085", 0, 200, "GPP_S" }, + { "INTC1085", 1, 208, "GPP_E" }, + { "INTC1085", 2, 231, "GPP_K" }, + { "INTC1085", 3, 246, "GPP_F" }, + { "INTC1085", 0, 270, "GPP_D" }, + { "INTC1085", 1, 295, "JTAG" }, /* Lewisburg */ - { "INT3536", 0, 7, "" }, + { "INT3536", 0, 0, "" }, /* Emmitsburg */ - { "INTC1071", 0, 0, "GPP_A" }, + { "INTC1071", 0, 0, "GPP_A" }, { "INTC1071", 1, 21, "GPP_B" }, { "INTC1071", 2, 45, "SPI" }, { "INTC1071", 0, 66, "GPP_C" }, { "INTC1071", 1, 88, "GPP_D" }, - { "INTC1071", 0, 112, "GPP_E" }, - { "INTC1071", 1, 136, "JTAG" }, - { "INTC1071", 0, 146, "GPP_H" }, - { "INTC1071", 1, 166, "GPP_J" }, - { "INTC1071", 0, 184, "GPP_I" }, - { "INTC1071", 1, 208, "GPP_L" }, - { "INTC1071", 2, 226, "GPP_M" }, - { "INTC1071", 3, 244, "GPP_N" }, + { "INTC1071", 0, 112, "GPP_E" }, + { "INTC1071", 1, 136, "JTAG" }, + { "INTC1071", 0, 146, "GPP_H" }, + { "INTC1071", 1, 166, "GPP_J" }, + { "INTC1071", 0, 184, "GPP_I" }, + { "INTC1071", 1, 208, "GPP_L" }, + { "INTC1071", 2, 226, "GPP_M" }, + { "INTC1071", 3, 244, "GPP_N" }, /* Denverton */ - { "INTC3000", 0, 0, "North" }, - { "INTC3000", 1, 32, "North" }, - { "INTC3000", 0, 41, "South" }, - { "INTC3000", 1, 59, "South" }, - { "INTC3000", 2, 91, "South" }, - { "INTC3000", 3, 112, "South" }, - { "INTC3000", 4, 144, "South" }, - + { "INTC3000", 0, 0, "North_ALL_0" }, + { "INTC3000", 1, 32, "North_ALL_1" }, + { "INTC3000", 0, 41, "South_DFX" }, + { "INTC3000", 1, 59, "South_GPP0_0" }, + { "INTC3000", 2, 91, "South_GPP0_1" }, + { "INTC3000", 3, 112, "South_GPP1_0" }, + { "INTC3000", 4, 144, "South_GPP1_1" }, /* Cedarfork */ - { "INTC3001", 0, 0, "WEST2" }, + { "INTC3001", 0, 0, "WEST2" }, { "INTC3001", 1, 24, "WEST3" }, { "INTC3001", 2, 48, "WEST01" }, { "INTC3001", 3, 71, "WEST5" }, { "INTC3001", 4, 91, "WESTC" }, { "INTC3001", 5, 97, "WESTC_DFX" }, - { "INTC3001", 6, 102, "WESTA" }, - { "INTC3001", 7, 112, "WESTB" }, - { "INTC3001", 8, 124, "WESTD" }, - { "INTC3001", 9, 144, "WESTD_PECI" }, - { "INTC3001", 10, 145, "WESTF" }, - { "INTC3001", 0, 168, "EAST2" }, - { "INTC3001", 1, 192, "EAST3" }, - { "INTC3001", 2, 203, "EAST0" }, - { "INTC3001", 3, 226, "EMMC" }, + { "INTC3001", 6, 102, "WESTA" }, + { "INTC3001", 7, 112, "WESTB" }, + { "INTC3001", 8, 124, "WESTD" }, + { "INTC3001", 9, 144, "WESTD_PECI" }, + { "INTC3001", 10, 145, "WESTF" }, + { "INTC3001", 0, 168, "EAST2" }, + { "INTC3001", 1, 192, "EAST3" }, + { "INTC3001", 2, 203, "EAST0" }, + { "INTC3001", 3, 226, "EMMC" }, - /* Geminilake */ - { "INT3453", 0, 34, "" }, + /* Gemini Lake */ + { "INT3453", 0, 34, "" }, #ifdef notyet /* @@ -479,14 +522,14 @@ struct igpio_pin_group igpio_pin_group[] /* Broxton */ { "apollolake-pinctrl", 0, 0, "" }, { "broxton-pinctrl", 0, 0, "" }, - { "INT34D1", 0, 0, "" }, - { "INT3452", 0, 0, "" }, + { "INT34D1", 0, 0, "" }, + { "INT3452", 0, 0, "" }, /* Cherryview */ - { "INT33FF", 0, 0, "" }, + { "INT33FF", 0, 0, "" }, #endif - { NULL, 0, 0, 0 }, + { NULL, 0, 0, 0 }, }; #endif /* _IGPIOREG_H */ Index: src/sys/dev/ic/igpiovar.h diff -u src/sys/dev/ic/igpiovar.h:1.1 src/sys/dev/ic/igpiovar.h:1.1.4.1 --- src/sys/dev/ic/igpiovar.h:1.1 Thu Mar 24 02:24:25 2022 +++ src/sys/dev/ic/igpiovar.h Mon Jan 23 12:15:59 2023 @@ -1,4 +1,4 @@ -/* $NetBSD: igpiovar.h,v 1.1 2022/03/24 02:24:25 manu Exp $ */ +/* $NetBSD: igpiovar.h,v 1.1.4.1 2023/01/23 12:15:59 martin Exp $ */ /* * Copyright (c) 2021 Emmanuel Dreyfus @@ -31,7 +31,7 @@ struct igpio_softc { device_t sc_dev; - const char *sc_acpi_hid; + const char *sc_acpi_hid; bus_space_tag_t sc_bst; int sc_nbar; bus_addr_t *sc_base;