Module Name: src
Committed By: msaitoh
Date: Sat Jan 28 07:45:21 UTC 2023
Modified Files:
src/sys/arch/x86/pci: amdzentemp.c
Log Message:
Reduce diff against DragonFly. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/x86/pci/amdzentemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/pci/amdzentemp.c
diff -u src/sys/arch/x86/pci/amdzentemp.c:1.16 src/sys/arch/x86/pci/amdzentemp.c:1.17
--- src/sys/arch/x86/pci/amdzentemp.c:1.16 Thu Nov 24 21:03:38 2022
+++ src/sys/arch/x86/pci/amdzentemp.c Sat Jan 28 07:45:21 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ */
+/* $NetBSD: amdzentemp.c,v 1.17 2023/01/28 07:45:21 msaitoh Exp $ */
/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
/*
@@ -53,7 +53,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.16 2022/11/24 21:03:38 mrg Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdzentemp.c,v 1.17 2023/01/28 07:45:21 msaitoh Exp $ ");
#include <sys/param.h>
#include <sys/bus.h>
@@ -74,7 +74,6 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
#include "amdsmn.h"
#define AMD_CURTMP_RANGE_ADJUST 49000000 /* in microKelvins (ie, 49C) */
-#define AMD_CURTMP_RANGE_CHECK __BIT(19)
#define F10_TEMP_CURTMP __BITS(31,21) /* XXX same as amdtemp.c */
#define F10_TEMP_CURTMP_MASK 0x7ff
#define F15M60_CURTMP_TJSEL __BITS(17,16)
@@ -96,14 +95,7 @@ __KERNEL_RCSID(0, "$NetBSD: amdzentemp.c
* to -49..206C.
*/
#define AMD_17H_CUR_TMP 0x59800
-
-/*
- * The following register set was discovered experimentally by Ondrej Čerman
- * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
- * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
- * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
- */
-#define AMD_17H_CCD_TMP_BASE 0x59954
+#define AMD_17H_CUR_TMP_RANGE_SEL __BIT(19)
#define AMD_17H_CCD_TMP_VALID __BIT(11)
struct amdzentemp_softc {
@@ -114,7 +106,7 @@ struct amdzentemp_softc {
size_t sc_sensor_len;
size_t sc_numsensors;
int32_t sc_offset;
- uint32_t sc_ccd_tmp_base;
+ int32_t sc_ccd_offset;
};
enum {
@@ -339,14 +331,16 @@ amdzentemp_family17_refresh(struct sysmo
edata->state = ENVSYS_SINVALID;
return;
}
- minus49 = (temp & AMD_CURTMP_RANGE_CHECK) ? true : false;
+ minus49 = (temp & AMD_17H_CUR_TMP_RANGE_SEL) ?
+ true : false;
temp = __SHIFTOUT(temp, F10_TEMP_CURTMP);
break;
case CCD_BASE ... (CCD_MAX - 1):
/* Tccd */
i = edata->private - CCD_BASE;
error = amdsmn_read(sc->sc_smn,
- sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
+ AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+ &temp);
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID)) {
edata->state = ENVSYS_SINVALID;
return;
@@ -372,6 +366,8 @@ amdzentemp_probe_ccd_sensors17h(struct a
{
int maxreg;
+ sc->sc_ccd_offset = 0x154;
+
switch (model) {
case 0x00 ... 0x2f: /* Zen1, Zen+ */
maxreg = 4;
@@ -399,10 +395,11 @@ amdzentemp_probe_ccd_sensors19h(struct a
case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
case 0x50 ... 0x5f: /* Zen3 Ryzen "Cezanne" */
+ sc->sc_ccd_offset = 0x154;
maxreg = 8;
break;
case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
- sc->sc_ccd_tmp_base = 0x59b08;
+ sc->sc_ccd_offset = 0x308;
maxreg = 8;
break;
default:
@@ -419,9 +416,6 @@ amdzentemp_probe_ccd_sensors(struct amdz
{
int nccd;
- /* Set default CCD temp sensor base address. */
- sc->sc_ccd_tmp_base = 0x59954;
-
switch (family) {
case 0x17:
nccd = amdzentemp_probe_ccd_sensors17h(sc, model);
@@ -446,7 +440,8 @@ amdzentemp_setup_ccd_sensors(struct amdz
for (i = 0; i < sc->sc_numsensors - 1; i++) {
error = amdsmn_read(sc->sc_smn,
- sc->sc_ccd_tmp_base + (i * sizeof(temp)), &temp);
+ AMD_17H_CUR_TMP + sc->sc_ccd_offset + (i * sizeof(temp)),
+ &temp);
if (error || !ISSET(temp, AMD_17H_CCD_TMP_VALID))
continue;
