Module Name: src
Committed By: riastradh
Date: Thu Feb 23 14:56:37 UTC 2023
Modified Files:
src/sys/arch/sparc/sparc: locore.s
Log Message:
sparc: Add missing barriers in cpu_switchto.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.283 -r1.284 src/sys/arch/sparc/sparc/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc/sparc/locore.s
diff -u src/sys/arch/sparc/sparc/locore.s:1.283 src/sys/arch/sparc/sparc/locore.s:1.284
--- src/sys/arch/sparc/sparc/locore.s:1.283 Sun May 15 02:14:15 2022
+++ src/sys/arch/sparc/sparc/locore.s Thu Feb 23 14:56:37 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.283 2022/05/15 02:14:15 mrg Exp $ */
+/* $NetBSD: locore.s,v 1.284 2023/02/23 14:56:37 riastradh Exp $ */
/*
* Copyright (c) 1996 Paul Kranenburg
@@ -4889,7 +4889,30 @@ Lwb1: SAVE; SAVE; SAVE; SAVE; SAVE; SAVE
/* set new cpcb, and curlwp */
sethi %hi(curlwp), %l7
st %g5, [%l6 + %lo(cpcb)] ! cpcb = newpcb;
+
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ * CPUs before we set ci_curlwp := newlwp on this one,
+ * requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ * before any subsequent mutex_exit by newlwp can even test
+ * whether there might be waiters, requiring a
+ * store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+ /* stbar -- store-before-store, not needed on TSO */
st %g3, [%l7 + %lo(curlwp)] ! curlwp = l;
+#ifdef MULTIPROCESSOR
+ ldstub [%sp - 4], %g0 /* makeshift store-before-load barrier */
+#endif
/* compute new wim */
ld [%g5 + PCB_WIM], %o0
