Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:24 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: cpu_switch.S
Log Message:
riscv: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/cpu_switch.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/cpu_switch.S
diff -u src/sys/arch/riscv/riscv/cpu_switch.S:1.3 src/sys/arch/riscv/riscv/cpu_switch.S:1.4
--- src/sys/arch/riscv/riscv/cpu_switch.S:1.3 Thu Feb 23 14:56:23 2023
+++ src/sys/arch/riscv/riscv/cpu_switch.S Wed Mar 1 08:18:24 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_switch.S,v 1.3 2023/02/23 14:56:23 riastradh Exp $ */
+/* $NetBSD: cpu_switch.S,v 1.4 2023/03/01 08:18:24 riastradh Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -177,7 +177,13 @@ ENTRY_NP(cpu_fast_switchto)
mv tp, a0 // set thread pointer to newlwp
fence w,w // for mutex_enter; see cpu_switchto
PTR_S tp, CI_CURLWP(t1) // update curlwp
- fence w,r // for mutex_enter; see cpu_switchto
+ /*
+ * No need for barrier after ci->ci_curlwp = softlwp -- when we
+ * enter a softint lwp, it can't be holding any mutexes, so it
+ * can't release any until after it has acquired them, so we
+ * need not participate in the protocol with mutex_vector_enter
+ * barriers here.
+ */
PTR_L sp, L_MD_KTF(tp) // switch to its stack
csrw sstatus, t0 // reenable interrupts
call _C_LABEL(softint_dispatch)
