Module Name: src
Committed By: riastradh
Date: Wed Mar 1 08:18:39 UTC 2023
Modified Files:
src/sys/arch/sparc64/sparc64: locore.s
Log Message:
sparc64: Optimization: Omit needless membar when triggering softint.
When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
To generate a diff of this commit:
cvs rdiff -u -r1.432 -r1.433 src/sys/arch/sparc64/sparc64/locore.s
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc64/sparc64/locore.s
diff -u src/sys/arch/sparc64/sparc64/locore.s:1.432 src/sys/arch/sparc64/sparc64/locore.s:1.433
--- src/sys/arch/sparc64/sparc64/locore.s:1.432 Thu Feb 23 14:56:56 2023
+++ src/sys/arch/sparc64/sparc64/locore.s Wed Mar 1 08:18:39 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.432 2023/02/23 14:56:56 riastradh Exp $ */
+/* $NetBSD: locore.s,v 1.433 2023/03/01 08:18:39 riastradh Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@@ -6847,7 +6847,13 @@ ENTRY(softint_fastintr)
or %o3, %lo(USPACE - TF_SIZE - CC64FSZ - STKB), %o3
membar #StoreStore /* for mutex_enter; see cpu_switchto */
STPTR %i0, [%l7 + %lo(CURLWP)]
- membar #StoreLoad /* for mutex_enter; see cpu_switchto */
+ /*
+ * No need for barrier after ci->ci_curlwp = softlwp -- when we
+ * enter a softint lwp, it can't be holding any mutexes, so it
+ * can't release any until after it has acquired them, so we
+ * need not participate in the protocol with mutex_vector_enter
+ * barriers here.
+ */
add %l1, %o3, %i6
STPTR %l1, [%l6 + %lo(CPCB)]
stx %i6, [%l1 + PCB_SP]
