Module Name: src
Committed By: andvar
Date: Sat May 6 21:37:37 UTC 2023
Modified Files:
src/sys/arch/arm/at91: at91twireg.h
Log Message:
s/Registre/Register/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/at91/at91twireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/at91/at91twireg.h
diff -u src/sys/arch/arm/at91/at91twireg.h:1.2 src/sys/arch/arm/at91/at91twireg.h:1.3
--- src/sys/arch/arm/at91/at91twireg.h:1.2 Thu Jul 3 01:15:38 2008
+++ src/sys/arch/arm/at91/at91twireg.h Sat May 6 21:37:37 2023
@@ -1,5 +1,5 @@
-/* $Id: at91twireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
-/* $NetBSD: at91twireg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
+/* $Id: at91twireg.h,v 1.3 2023/05/06 21:37:37 andvar Exp $ */
+/* $NetBSD: at91twireg.h,v 1.3 2023/05/06 21:37:37 andvar Exp $ */
/*-
* Copyright (c) 2007 Embedtronics Oy.
@@ -54,7 +54,7 @@
#define TWI_RHR 0x30U /* 0x30: Receive Holding Register */
#define TWI_THR 0x34U /* 0x34: Transmit Holding Register */
-/* Control Registre bits: */
+/* Control Register bits: */
#define TWI_CR_SWRST 0x80U /* 1 = do software reset */
#define TWI_CR_MSDIS 0x08U /* 1 = disable master mode */
#define TWI_CR_MSEN 0x04U /* 1 = enable master mode */
