Module Name: src
Committed By: msaitoh
Date: Thu Jul 13 09:12:24 UTC 2023
Modified Files:
src/sys/arch/x86/x86: coretemp.c
Log Message:
coretemp(4): Change limits of Tjmax.
- Change the lower limit from 70 to 60. At least, some BIOSes can change
the value down to 62.
- Change the upper limit from 110 to 120. At least, some BIOSes can change
the value up to 115.
- Print error message when rdmsr(TEMPERATURE_TARGET) failed.
- When Tjmax exceeded the limit, print warning message and use the value
as it is.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/x86/x86/coretemp.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/x86/coretemp.c
diff -u src/sys/arch/x86/x86/coretemp.c:1.38 src/sys/arch/x86/x86/coretemp.c:1.39
--- src/sys/arch/x86/x86/coretemp.c:1.38 Thu Oct 7 12:52:27 2021
+++ src/sys/arch/x86/x86/coretemp.c Thu Jul 13 09:12:23 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: coretemp.c,v 1.38 2021/10/07 12:52:27 msaitoh Exp $ */
+/* $NetBSD: coretemp.c,v 1.39 2023/07/13 09:12:23 msaitoh Exp $ */
/*-
* Copyright (c) 2011 The NetBSD Foundation, Inc.
@@ -61,7 +61,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.38 2021/10/07 12:52:27 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: coretemp.c,v 1.39 2023/07/13 09:12:23 msaitoh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -102,6 +102,10 @@ __KERNEL_RCSID(0, "$NetBSD: coretemp.c,v
#define MSR_TEMP_TARGET_READOUT __BITS(16, 23)
+#define TJMAX_DEFAULT 100
+#define TJMAX_LIMIT_LOW 60
+#define TJMAX_LIMIT_HIGH 120
+
static int coretemp_match(device_t, cfdata_t, void *);
static void coretemp_attach(device_t, device_t, void *);
static int coretemp_detach(device_t, int);
@@ -259,16 +263,15 @@ coretemp_tjmax(device_t self)
{
struct coretemp_softc *sc = device_private(self);
struct cpu_info *ci = sc->sc_ci;
- uint32_t model, stepping;
uint64_t msr;
+ uint32_t model, stepping;
+ int tjmax;
model = CPUID_TO_MODEL(ci->ci_signature);
stepping = CPUID_TO_STEPPING(ci->ci_signature);
- /*
- * Use 100C as the initial value.
- */
- sc->sc_tjmax = 100;
+ /* Set the initial value. */
+ sc->sc_tjmax = TJMAX_DEFAULT;
if ((model == 0x0f && stepping >= 2) || (model == 0x0e)) {
/*
@@ -304,20 +307,20 @@ coretemp_tjmax(device_t self)
sc->sc_tjmax = 90;
} else {
notee:
- /*
- * Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET,
- * but only consider the interval [70, 110] C as valid.
- * It is not fully known which CPU models have the MSR.
- */
- if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT)
- return;
-
- msr = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
-
- if (msr >= 70 && msr <= 110) {
- sc->sc_tjmax = msr;
+ /* Attempt to get Tj(max) from IA32_TEMPERATURE_TARGET. */
+ if (rdmsr_safe(MSR_TEMPERATURE_TARGET, &msr) == EFAULT) {
+ aprint_error_dev(sc->sc_dev,
+ "Failed to read TEMPERATURE_TARGET MSR. "
+ "Use the default (%d)\n", sc->sc_tjmax);
return;
}
+
+ tjmax = __SHIFTOUT(msr, MSR_TEMP_TARGET_READOUT);
+ if ((tjmax < TJMAX_LIMIT_LOW) || (tjmax > TJMAX_LIMIT_HIGH))
+ aprint_error_dev(sc->sc_dev,
+ "WARNING: Tjmax(%d) might exceeded the limit.\n",
+ tjmax);
+ sc->sc_tjmax = tjmax;
}
}
