Module Name: src
Committed By: martin
Date: Mon Jul 31 14:26:26 UTC 2023
Modified Files:
src/sys/arch/alpha/alpha [netbsd-8]: locore.s multiproc.s
src/sys/arch/arm/cortex [netbsd-8]: a9_mpsubr.S cortex_init.S
Log Message:
Pull up following revision(s) (requested by riastradh in ticket #1859):
sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
sys/arch/aarch64/aarch64/locore.S: revision 1.91
sys/arch/mips/include/asm.h: revision 1.74
sys/arch/hppa/include/cpu.h: revision 1.13
sys/arch/arm/arm/armv6_start.S: revision 1.38
(applied also to sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/a9_mpsubr.S,
sys/arch/arm/cortex/cortex_init.S)
sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
sys/arch/mips/mips/locore.S: revision 1.229
sys/arch/alpha/include/asm.h: revision 1.45
(applied to sys/arch/alpha/alpha/multiproc.s)
sys/arch/sparc64/sparc64/locore.s: revision 1.432
sys/arch/vax/vax/subr.S: revision 1.42
sys/arch/mips/mips/locore_mips3.S: revision 1.116
sys/arch/ia64/ia64/machdep.c: revision 1.44
sys/arch/arm/arm32/cpuswitch.S: revision 1.106
sys/arch/sparc/sparc/locore.s: revision 1.284
(all via patch)
aarch64: Add missing barriers in cpu_switchto.
Details in comments.
Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.
PR kern/57240
alpha: Add missing barriers in cpu_switchto.
Details in comments.
arm32: Add missing barriers in cpu_switchto.
Details in comments.
hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?
ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)
mips: Add missing barriers in cpu_switchto.
Details in comments.
powerpc: Add missing barriers in cpu_switchto.
Details in comments.
sparc: Add missing barriers in cpu_switchto.
sparc64: Add missing barriers in cpu_switchto.
Details in comments.
vax: Note where cpu_switchto needs barriers.
Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.
To generate a diff of this commit:
cvs rdiff -u -r1.122 -r1.122.32.1 src/sys/arch/alpha/alpha/locore.s
cvs rdiff -u -r1.13 -r1.13.80.1 src/sys/arch/alpha/alpha/multiproc.s
cvs rdiff -u -r1.47.8.2 -r1.47.8.3 src/sys/arch/arm/cortex/a9_mpsubr.S
cvs rdiff -u -r1.1 -r1.1.12.1 src/sys/arch/arm/cortex/cortex_init.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/alpha/alpha/locore.s
diff -u src/sys/arch/alpha/alpha/locore.s:1.122 src/sys/arch/alpha/alpha/locore.s:1.122.32.1
--- src/sys/arch/alpha/alpha/locore.s:1.122 Sun Feb 19 21:05:58 2012
+++ src/sys/arch/alpha/alpha/locore.s Mon Jul 31 14:26:25 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.122 2012/02/19 21:05:58 rmind Exp $ */
+/* $NetBSD: locore.s,v 1.122.32.1 2023/07/31 14:26:25 martin Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -67,7 +67,7 @@
#include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.122 2012/02/19 21:05:58 rmind Exp $");
+__KERNEL_RCSID(0, "$NetBSD: locore.s,v 1.122.32.1 2023/07/31 14:26:25 martin Exp $");
#include "assym.h"
@@ -686,8 +686,28 @@ LEAF(cpu_switchto, 0)
SWITCH_CONTEXT /* swap the context */
- GET_CPUINFO
+ /*
+ * Issue barriers to coordinate mutex_exit on this CPU with
+ * mutex_vector_enter on another CPU.
+ *
+ * 1. Any prior mutex_exit by oldlwp must be visible to other
+ * CPUs before we set ci_curlwp := newlwp on this one,
+ * requiring a store-before-store barrier.
+ *
+ * 2. ci_curlwp := newlwp must be visible on all other CPUs
+ * before any subsequent mutex_exit by newlwp can even test
+ * whether there might be waiters, requiring a
+ * store-before-load barrier.
+ *
+ * See kern_mutex.c for details -- this is necessary for
+ * adaptive mutexes to detect whether the lwp is on the CPU in
+ * order to safely block without requiring atomic r/m/w in
+ * mutex_exit.
+ */
+ GET_CPUINFO /* v0 = curcpu() */
+ wmb /* store-before-store XXX patch out if !MP? */
stq s2, CPU_INFO_CURLWP(v0) /* curlwp = l */
+ mb /* store-before-load XXX patch out if !MP? */
/*
* Now running on the new PCB.
Index: src/sys/arch/alpha/alpha/multiproc.s
diff -u src/sys/arch/alpha/alpha/multiproc.s:1.13 src/sys/arch/alpha/alpha/multiproc.s:1.13.80.1
--- src/sys/arch/alpha/alpha/multiproc.s:1.13 Mon Apr 28 20:23:10 2008
+++ src/sys/arch/alpha/alpha/multiproc.s Mon Jul 31 14:26:25 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: multiproc.s,v 1.13 2008/04/28 20:23:10 martin Exp $ */
+/* $NetBSD: multiproc.s,v 1.13.80.1 2023/07/31 14:26:25 martin Exp $ */
/*-
* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-__KERNEL_RCSID(5, "$NetBSD: multiproc.s,v 1.13 2008/04/28 20:23:10 martin Exp $")
+__KERNEL_RCSID(5, "$NetBSD: multiproc.s,v 1.13.80.1 2023/07/31 14:26:25 martin Exp $")
/*
* Multiprocessor glue code.
@@ -65,6 +65,11 @@ NESTED_NOPROFILE(cpu_spinup_trampoline,0
/* Switch to this CPU's idle thread. */
ldq a0, CPU_INFO_IDLE_LWP(s0)
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
stq a0, CPU_INFO_CURLWP(s0) /* set curlwp */
ldq a0, L_MD_PCBPADDR(a0)
SWITCH_CONTEXT
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.47.8.2 src/sys/arch/arm/cortex/a9_mpsubr.S:1.47.8.3
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.47.8.2 Fri Nov 17 15:07:16 2017
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Mon Jul 31 14:26:25 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.47.8.2 2017/11/17 15:07:16 martin Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.47.8.3 2023/07/31 14:26:25 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -771,6 +771,11 @@ cortex_mpcontinuation:
#else
#error either TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP must be defined
#endif
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
str r6, [r5, #CI_CURLWP] // and note we are running on it
#ifdef MPDEBUG
Index: src/sys/arch/arm/cortex/cortex_init.S
diff -u src/sys/arch/arm/cortex/cortex_init.S:1.1 src/sys/arch/arm/cortex/cortex_init.S:1.1.12.1
--- src/sys/arch/arm/cortex/cortex_init.S:1.1 Wed Nov 25 04:03:34 2015
+++ src/sys/arch/arm/cortex/cortex_init.S Mon Jul 31 14:26:25 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: cortex_init.S,v 1.1 2015/11/25 04:03:34 marty Exp $ */
+/* $NetBSD: cortex_init.S,v 1.1.12.1 2023/07/31 14:26:25 martin Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -728,6 +728,11 @@ cortex_mpcontinuation:
#else
#error either TPIDRPRW_IS_CURCPU or TPIDRPRW_IS_CURLWP must be defined
#endif
+ /*
+ * No membar needed because we're not switching from a
+ * previous lwp, and the idle lwp we're switching to can't be
+ * holding locks already; see cpu_switchto.
+ */
str r6, [r5, #CI_CURLWP] // and note we are running on it
#ifdef MPDEBUG
