Module Name: src
Committed By: martin
Date: Tue Aug 1 17:34:33 UTC 2023
Modified Files:
src/sys/dev/tprof [netbsd-9]: tprof.c tprof_x86_amd.c tprof_x86_intel.c
src/usr.sbin/tprof [netbsd-9]: tprof.8 tprof_analyze.c
src/usr.sbin/tprof/arch [netbsd-9]: tprof_x86.c
Log Message:
Pull up the following revisions, requested by msaitoh in ticket #1697:
usr.sbin/tprof/tprof.8 1.16,1.22,1.25,1.29 via
patch
usr.sbin/tprof/tprof_analyze.c 1.4
usr.sbin/tprof/arch/tprof_x86.c 1.13-1.19
sys/dev/tprof/tprof.c 1.23 via patch
sys/dev/tprof/tprof_x86_amd.c 1.7-1.8 via patch
sys/dev/tprof/tprof_x86_intel.c 1.8 via patch
- Add AMD family 19h (zen3 and zen4) support.
- Add Intel Comet Lake support.
- Add support for Intel Skylake-X and Cascade Lake.
- Print the path that we failed to open on error.
- Use lowercase consistently for hexadecimal numbers.
- KNF
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.14.6.1 src/sys/dev/tprof/tprof.c
cvs rdiff -u -r1.4.2.1 -r1.4.2.2 src/sys/dev/tprof/tprof_x86_amd.c
cvs rdiff -u -r1.3.2.1 -r1.3.2.2 src/sys/dev/tprof/tprof_x86_intel.c
cvs rdiff -u -r1.14.2.1 -r1.14.2.2 src/usr.sbin/tprof/tprof.8
cvs rdiff -u -r1.3 -r1.3.6.1 src/usr.sbin/tprof/tprof_analyze.c
cvs rdiff -u -r1.8.4.2 -r1.8.4.3 src/usr.sbin/tprof/arch/tprof_x86.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/dev/tprof/tprof.c
diff -u src/sys/dev/tprof/tprof.c:1.14 src/sys/dev/tprof/tprof.c:1.14.6.1
--- src/sys/dev/tprof/tprof.c:1.14 Fri Jul 13 07:56:29 2018
+++ src/sys/dev/tprof/tprof.c Tue Aug 1 17:34:33 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof.c,v 1.14 2018/07/13 07:56:29 maxv Exp $ */
+/* $NetBSD: tprof.c,v 1.14.6.1 2023/08/01 17:34:33 martin Exp $ */
/*-
* Copyright (c)2008,2009,2010 YAMAMOTO Takashi,
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof.c,v 1.14 2018/07/13 07:56:29 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof.c,v 1.14.6.1 2023/08/01 17:34:33 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -178,7 +178,7 @@ tprof_worker(struct work *wk, void *dumm
KASSERT(dummy == NULL);
/*
- * get a per cpu buffer.
+ * Get a per cpu buffer.
*/
buf = tprof_buf_refresh();
@@ -208,12 +208,11 @@ tprof_worker(struct work *wk, void *dumm
tprof_stat.ts_dropbuf++;
}
mutex_exit(&tprof_lock);
- if (buf) {
+ if (buf)
tprof_buf_free(buf);
- }
- if (!shouldstop) {
+
+ if (!shouldstop)
callout_schedule(&c->c_callout, hz);
- }
}
static void
@@ -239,9 +238,9 @@ tprof_stop1(void)
tprof_buf_t *old;
old = tprof_buf_switch(c, NULL);
- if (old != NULL) {
+ if (old != NULL)
tprof_buf_free(old);
- }
+
callout_destroy(&c->c_callout);
}
workqueue_destroy(tprof_wq);
@@ -256,9 +255,8 @@ tprof_getinfo(struct tprof_info *info)
memset(info, 0, sizeof(*info));
info->ti_version = TPROF_VERSION;
- if ((tb = tprof_backend) != NULL) {
+ if ((tb = tprof_backend) != NULL)
info->ti_ident = tb->tb_ops->tbo_ident();
- }
}
static int
@@ -351,9 +349,9 @@ tprof_stop(void)
mutex_enter(&tprof_lock);
tprof_running = false;
cv_broadcast(&tprof_reader_cv);
- while (tprof_nworker > 0) {
+ while (tprof_nworker > 0)
cv_wait(&tprof_cv, &tprof_lock);
- }
+
mutex_exit(&tprof_lock);
tprof_stop1();
@@ -451,9 +449,8 @@ tprof_backend_register(const char *name,
{
tprof_backend_t *tb;
- if (vers != TPROF_BACKEND_VERSION) {
+ if (vers != TPROF_BACKEND_VERSION)
return EINVAL;
- }
mutex_enter(&tprof_startstop_lock);
tb = tprof_backend_lookup(name);
@@ -504,9 +501,8 @@ tprof_backend_unregister(const char *nam
return EBUSY;
}
#if 1 /* XXX for now */
- if (tprof_backend == tb) {
+ if (tprof_backend == tb)
tprof_backend = NULL;
- }
#endif
LIST_REMOVE(tb, tb_list);
mutex_exit(&tprof_startstop_lock);
@@ -522,9 +518,9 @@ static int
tprof_open(dev_t dev, int flags, int type, struct lwp *l)
{
- if (minor(dev) != 0) {
+ if (minor(dev) != 0)
return EXDEV;
- }
+
mutex_enter(&tprof_lock);
if (tprof_owner != NULL) {
mutex_exit(&tprof_lock);
@@ -566,7 +562,7 @@ tprof_read(dev_t dev, struct uio *uio, i
mutex_enter(&tprof_reader_lock);
while (uio->uio_resid > 0 && error == 0) {
/*
- * take the first buffer from the list.
+ * Take the first buffer from the list.
*/
mutex_enter(&tprof_lock);
buf = STAILQ_FIRST(&tprof_list);
@@ -588,7 +584,7 @@ tprof_read(dev_t dev, struct uio *uio, i
mutex_exit(&tprof_lock);
/*
- * copy it out.
+ * Copy it out.
*/
bytes = MIN(buf->b_used * sizeof(tprof_sample_t) -
tprof_reader_offset, uio->uio_resid);
@@ -599,7 +595,7 @@ tprof_read(dev_t dev, struct uio *uio, i
tprof_reader_offset += done;
/*
- * if we didn't consume the whole buffer,
+ * If we didn't consume the whole buffer,
* put it back to the list.
*/
if (tprof_reader_offset <
@@ -676,7 +672,7 @@ void
tprofattach(int nunits)
{
- /* nothing */
+ /* Nothing */
}
MODULE(MODULE_CLASS_DRIVER, tprof, NULL);
Index: src/sys/dev/tprof/tprof_x86_amd.c
diff -u src/sys/dev/tprof/tprof_x86_amd.c:1.4.2.1 src/sys/dev/tprof/tprof_x86_amd.c:1.4.2.2
--- src/sys/dev/tprof/tprof_x86_amd.c:1.4.2.1 Sat Oct 12 14:34:45 2019
+++ src/sys/dev/tprof/tprof_x86_amd.c Tue Aug 1 17:34:33 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86_amd.c,v 1.4.2.1 2019/10/12 14:34:45 martin Exp $ */
+/* $NetBSD: tprof_x86_amd.c,v 1.4.2.2 2023/08/01 17:34:33 martin Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -56,7 +56,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof_x86_amd.c,v 1.4.2.1 2019/10/12 14:34:45 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof_x86_amd.c,v 1.4.2.2 2023/08/01 17:34:33 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -166,7 +166,7 @@ tprof_amd_nmi(const struct trapframe *tf
return 0;
}
- /* record a sample */
+ /* Record a sample */
#if defined(__x86_64__)
tfi.tfi_pc = tf->tf_rip;
#else
@@ -199,14 +199,14 @@ tprof_amd_ident(void)
{
struct cpu_info *ci = curcpu();
- if (cpu_vendor != CPUVENDOR_AMD) {
+ if (cpu_vendor != CPUVENDOR_AMD)
return TPROF_IDENT_NONE;
- }
switch (CPUID_TO_FAMILY(ci->ci_signature)) {
case 0x10:
case 0x15:
case 0x17:
+ case 0x19:
return TPROF_IDENT_AMD_GENERIC;
}
@@ -218,9 +218,8 @@ tprof_amd_start(const tprof_param_t *par
{
uint64_t xc;
- if (tprof_amd_ident() == TPROF_IDENT_NONE) {
+ if (tprof_amd_ident() == TPROF_IDENT_NONE)
return ENOTSUP;
- }
KASSERT(amd_nmi_handle == NULL);
amd_nmi_handle = nmi_establish(tprof_amd_nmi, NULL);
Index: src/sys/dev/tprof/tprof_x86_intel.c
diff -u src/sys/dev/tprof/tprof_x86_intel.c:1.3.2.1 src/sys/dev/tprof/tprof_x86_intel.c:1.3.2.2
--- src/sys/dev/tprof/tprof_x86_intel.c:1.3.2.1 Sat Oct 15 10:20:32 2022
+++ src/sys/dev/tprof/tprof_x86_intel.c Tue Aug 1 17:34:33 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86_intel.c,v 1.3.2.1 2022/10/15 10:20:32 martin Exp $ */
+/* $NetBSD: tprof_x86_intel.c,v 1.3.2.2 2023/08/01 17:34:33 martin Exp $ */
/*
* Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -56,7 +56,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof_x86_intel.c,v 1.3.2.1 2022/10/15 10:20:32 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof_x86_intel.c,v 1.3.2.2 2023/08/01 17:34:33 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -145,7 +145,7 @@ tprof_intel_nmi(const struct trapframe *
return 0;
}
- /* record a sample */
+ /* Record a sample */
#if defined(__x86_64__)
tfi.tfi_pc = tf->tf_rip;
#else
@@ -154,10 +154,10 @@ tprof_intel_nmi(const struct trapframe *
tfi.tfi_inkernel = tfi.tfi_pc >= VM_MIN_KERNEL_ADDRESS;
tprof_sample(NULL, &tfi);
- /* reset counter */
+ /* Reset counter */
wrmsr(MSR_PERFCTR0, counter_reset_val);
- /* unmask PMI */
+ /* Unmask PMI */
pcint = lapic_readreg(LAPIC_LVT_PCINT);
KASSERT((pcint & LAPIC_LVT_MASKED) != 0);
lapic_writereg(LAPIC_LVT_PCINT, pcint & ~LAPIC_LVT_MASKED);
@@ -183,20 +183,18 @@ tprof_intel_ident(void)
{
uint32_t descs[4];
- if (cpu_vendor != CPUVENDOR_INTEL) {
+ if (cpu_vendor != CPUVENDOR_INTEL)
return TPROF_IDENT_NONE;
- }
- if (cpuid_level < 0x0A) {
+ if (cpuid_level < 0x0a)
return TPROF_IDENT_NONE;
- }
- x86_cpuid(0x0A, descs);
- if ((descs[0] & CPUID_PERF_VERSION) == 0) {
+
+ x86_cpuid(0x0a, descs);
+ if ((descs[0] & CPUID_PERF_VERSION) == 0)
return TPROF_IDENT_NONE;
- }
- if ((descs[0] & CPUID_PERF_NGPPC) == 0) {
+
+ if ((descs[0] & CPUID_PERF_NGPPC) == 0)
return TPROF_IDENT_NONE;
- }
counter_bitwidth = __SHIFTOUT(descs[0], CPUID_PERF_NBWGPPC);
@@ -208,9 +206,8 @@ tprof_intel_start(const tprof_param_t *p
{
uint64_t xc;
- if (tprof_intel_ident() == TPROF_IDENT_NONE) {
+ if (tprof_intel_ident() == TPROF_IDENT_NONE)
return ENOTSUP;
- }
KASSERT(intel_nmi_handle == NULL);
intel_nmi_handle = nmi_establish(tprof_intel_nmi, NULL);
Index: src/usr.sbin/tprof/tprof.8
diff -u src/usr.sbin/tprof/tprof.8:1.14.2.1 src/usr.sbin/tprof/tprof.8:1.14.2.2
--- src/usr.sbin/tprof/tprof.8:1.14.2.1 Sat Oct 12 14:34:45 2019
+++ src/usr.sbin/tprof/tprof.8 Tue Aug 1 17:34:32 2023
@@ -1,4 +1,4 @@
-.\" $NetBSD: tprof.8,v 1.14.2.1 2019/10/12 14:34:45 martin Exp $
+.\" $NetBSD: tprof.8,v 1.14.2.2 2023/08/01 17:34:32 martin Exp $
.\"
.\" Copyright (c)2011 YAMAMOTO Takashi,
.\" All rights reserved.
@@ -24,7 +24,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.Dd October 11, 2019
+.Dd April 10, 2023
.Dt TPROF 8
.Os
.Sh NAME
@@ -37,7 +37,9 @@
.Sh DESCRIPTION
The
.Nm
-tool can be used to monitor hardware events (PMCs) during the execution of
+tool can be used to monitor hardware events
+.Tn ( PMC Ns s )
+during the execution of
certain commands.
.Pp
The
@@ -48,7 +50,7 @@ keeps recording samples from the kernel
and reports statistics to the standard error.
.Pp
The
-.Nm tprof
+.Xr tprof 4
pseudo driver and a suitable backend should be loaded beforehand.
.Pp
The
@@ -134,9 +136,11 @@ x86 AMD Family 15h
.It
x86 AMD Family 17h
.It
+x86 AMD Family 19h
+.It
x86 Intel Generic (all Intel CPUs)
.It
-x86 Intel Skylake/Kabylake
+x86 Intel Skylake, Kabylake and Cometlake
.It
x86 Intel Silvermont/Airmont
.It
@@ -148,7 +152,7 @@ x86 Intel Goldmont Plus
The
.Nm
utility reports the following statistics about the activities of the
-.Nm tprof
+.Xr tprof 4
pseudo driver.
.Bl -tag -width dropbuf_samples
.It sample
Index: src/usr.sbin/tprof/tprof_analyze.c
diff -u src/usr.sbin/tprof/tprof_analyze.c:1.3 src/usr.sbin/tprof/tprof_analyze.c:1.3.6.1
--- src/usr.sbin/tprof/tprof_analyze.c:1.3 Sat Jul 14 07:54:04 2018
+++ src/usr.sbin/tprof/tprof_analyze.c Tue Aug 1 17:34:32 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_analyze.c,v 1.3 2018/07/14 07:54:04 maxv Exp $ */
+/* $NetBSD: tprof_analyze.c,v 1.3.6.1 2023/08/01 17:34:32 martin Exp $ */
/*
* Copyright (c) 2010,2011,2012 YAMAMOTO Takashi,
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: tprof_analyze.c,v 1.3 2018/07/14 07:54:04 maxv Exp $");
+__RCSID("$NetBSD: tprof_analyze.c,v 1.3.6.1 2023/08/01 17:34:32 martin Exp $");
#endif /* not lint */
#include <assert.h>
@@ -112,7 +112,7 @@ ksymload(void)
fd = open(_PATH_KSYMS, O_RDONLY);
if (fd == -1) {
- err(EXIT_FAILURE, "open");
+ err(EXIT_FAILURE, "open " _PATH_KSYMS);
}
if (elf_version(EV_CURRENT) == EV_NONE) {
goto elffail;
Index: src/usr.sbin/tprof/arch/tprof_x86.c
diff -u src/usr.sbin/tprof/arch/tprof_x86.c:1.8.4.2 src/usr.sbin/tprof/arch/tprof_x86.c:1.8.4.3
--- src/usr.sbin/tprof/arch/tprof_x86.c:1.8.4.2 Sat Oct 15 10:20:32 2022
+++ src/usr.sbin/tprof/arch/tprof_x86.c Tue Aug 1 17:34:32 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_x86.c,v 1.8.4.2 2022/10/15 10:20:32 martin Exp $ */
+/* $NetBSD: tprof_x86.c,v 1.8.4.3 2023/08/01 17:34:32 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -60,7 +60,8 @@ struct event_table {
static struct event_table *cpuevents = NULL;
-static void x86_cpuid(unsigned int *eax, unsigned int *ebx,
+static void
+x86_cpuid(unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
{
asm volatile("cpuid"
@@ -71,21 +72,21 @@ static void x86_cpuid(unsigned int *eax,
: "0" (*eax), "2" (*ecx));
}
-/* -------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
/*
* Intel Architectural Version 1.
*/
static struct name_to_event intel_arch1_names[] = {
/* Event Name - Event Select - UMask */
- { "unhalted-core-cycles", 0x3C, 0x00, true },
- { "instruction-retired", 0xC0, 0x00, true },
- { "unhalted-reference-cycles", 0x3C, 0x01, true },
- { "llc-reference", 0x2E, 0x4F, true },
- { "llc-misses", 0x2E, 0x41, true },
- { "branch-instruction-retired", 0xC4, 0x00, true },
- { "branch-misses-retired", 0xC5, 0x00, true },
- { "topdown-slots", 0xA4, 0x01, true },
+ { "unhalted-core-cycles", 0x3c, 0x00, true },
+ { "instruction-retired", 0xc0, 0x00, true },
+ { "unhalted-reference-cycles", 0x3c, 0x01, true },
+ { "llc-reference", 0x2e, 0x4f, true },
+ { "llc-misses", 0x2e, 0x41, true },
+ { "branch-instruction-retired", 0xc4, 0x00, true },
+ { "branch-misses-retired", 0xc5, 0x00, true },
+ { "topdown-slots", 0xa4, 0x01, true },
};
static struct event_table intel_arch1 = {
@@ -103,7 +104,7 @@ init_intel_arch1(void)
struct event_table *table;
size_t i;
- eax = 0x0A;
+ eax = 0x0a;
ebx = 0;
ecx = 0;
edx = 0;
@@ -150,53 +151,53 @@ static struct name_to_event intel_silver
{ "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
{ "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
{ "PAGE_WALKS.WALKS", 0x05, 0x03, true },
- { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
- { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2e, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2e, 0x4f, true },
{ "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
{ "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
- { "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
- { "CPU_CLK_UNHALTED.REF_P", 0x3C, 0x01, true },
+ { "CPU_CLK_UNHALTED.CORE_P", 0x3c, 0x00, true },
+ { "CPU_CLK_UNHALTED.REF_P", 0x3c, 0x01, true },
{ "ICACHE.HIT", 0x80, 0x01, true },
{ "ICACHE.MISSES", 0x80, 0x02, true },
{ "ICACHE.ACCESSES", 0x80, 0x03, true },
- { "OFFCORE_RESPONSE_0", 0xB7, 0x01, true },
- { "OFFCORE_RESPONSE_1", 0xB7, 0x02, true },
- { "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
- { "UOPS_RETIRED.MS", 0xC2, 0x01, true },
- { "UOPS_RETIRED.ALL", 0xC2, 0x10, true },
- { "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
- { "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
- { "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
- { "MACHINE_CLEARS.ALL", 0xC3, 0x08, true },
- { "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
- { "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
- { "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
- { "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
- { "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
- { "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
- { "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
- { "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
- { "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
- { "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
- { "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
- { "BR_MISP_RETIRED.FAR", 0xC5, 0xBF, true },
- { "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
- { "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
- { "BR_MISP_RETIRED.CALL", 0xC5, 0xF9, true },
- { "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
- { "BR_MISP_RETIRED.REL_CALL", 0xC5, 0xFD, true },
- { "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
- { "NO_ALLOC_CYCLES.ROB_FULL", 0xCA, 0x01, true },
- { "NO_ALLOC_CYCLES.RAT_STALL", 0xCA, 0x20, true },
- { "NO_ALLOC_CYCLES.ALL", 0xCA, 0x3F, true },
- { "NO_ALLOC_CYCLES.NOT_DELIVERED", 0xCA, 0x50, true },
- { "RS_FULL_STALL.MEC", 0xCB, 0x01, true },
- { "RS_FULL_STALL.ALL", 0xCB, 0x1F, true },
- { "CYCLES_DIV_BUSY.ANY", 0xCD, 0x01, true },
- { "BACLEARS.ALL", 0xE6, 0x01, true },
- { "BACLEARS.RETURN", 0xE6, 0x08, true },
- { "BACLEARS.COND", 0xE6, 0x10, true },
- { "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
+ { "OFFCORE_RESPONSE_0", 0xb7, 0x01, true },
+ { "OFFCORE_RESPONSE_1", 0xb7, 0x02, true },
+ { "INST_RETIRED.ANY_P", 0xc0, 0x00, true },
+ { "UOPS_RETIRED.MS", 0xc2, 0x01, true },
+ { "UOPS_RETIRED.ALL", 0xc2, 0x10, true },
+ { "MACHINE_CLEARS.SMC", 0xc3, 0x01, true },
+ { "MACHINE_CLEARS.MEMORY_ORDERING", 0xc3, 0x02, true },
+ { "MACHINE_CLEARS.FP_ASSIST", 0xc3, 0x04, true },
+ { "MACHINE_CLEARS.ALL", 0xc3, 0x08, true },
+ { "BR_INST_RETIRED.ALL_BRANCHES", 0xc4, 0x00, true },
+ { "BR_INST_RETIRED.JCC", 0xc4, 0x7e, true },
+ { "BR_INST_RETIRED.FAR_BRANCH", 0xc4, 0xbf, true },
+ { "BR_INST_RETIRED.NON_RETURN_IND", 0xc4, 0xeb, true },
+ { "BR_INST_RETIRED.RETURN", 0xc4, 0xf7, true },
+ { "BR_INST_RETIRED.CALL", 0xc4, 0xf9, true },
+ { "BR_INST_RETIRED.IND_CALL", 0xc4, 0xfb, true },
+ { "BR_INST_RETIRED.REL_CALL", 0xc4, 0xfd, true },
+ { "BR_INST_RETIRED.TAKEN_JCC", 0xc4, 0xfe, true },
+ { "BR_MISP_RETIRED.ALL_BRANCHES", 0xc5, 0x00, true },
+ { "BR_MISP_RETIRED.JCC", 0xc5, 0x7e, true },
+ { "BR_MISP_RETIRED.FAR", 0xc5, 0xbf, true },
+ { "BR_MISP_RETIRED.NON_RETURN_IND", 0xc5, 0xeb, true },
+ { "BR_MISP_RETIRED.RETURN", 0xc5, 0xf7, true },
+ { "BR_MISP_RETIRED.CALL", 0xc5, 0xf9, true },
+ { "BR_MISP_RETIRED.IND_CALL", 0xc5, 0xfb, true },
+ { "BR_MISP_RETIRED.REL_CALL", 0xc5, 0xfd, true },
+ { "BR_MISP_RETIRED.TAKEN_JCC", 0xc5, 0xfe, true },
+ { "NO_ALLOC_CYCLES.ROB_FULL", 0xca, 0x01, true },
+ { "NO_ALLOC_CYCLES.RAT_STALL", 0xca, 0x20, true },
+ { "NO_ALLOC_CYCLES.ALL", 0xca, 0x3f, true },
+ { "NO_ALLOC_CYCLES.NOT_DELIVERED", 0xca, 0x50, true },
+ { "RS_FULL_STALL.MEC", 0xcb, 0x01, true },
+ { "RS_FULL_STALL.ALL", 0xcb, 0x1f, true },
+ { "CYCLES_DIV_BUSY.ANY", 0xcd, 0x01, true },
+ { "BACLEARS.ALL", 0xe6, 0x01, true },
+ { "BACLEARS.RETURN", 0xe6, 0x08, true },
+ { "BACLEARS.COND", 0xe6, 0x10, true },
+ { "MS_DECODED.MS_ENTRY", 0xe7, 0x01, true },
};
static struct event_table intel_silvermont_airmont = {
@@ -226,15 +227,15 @@ static struct name_to_event intel_goldmo
{ "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
{ "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
{ "PAGE_WALKS.CYCLES", 0x05, 0x03, true },
- { "UOPS_ISSUED.ANY", 0x0E, 0x00, true },
+ { "UOPS_ISSUED.ANY", 0x0e, 0x00, true },
{ "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", 0x13, 0x02, true },
{ "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", 0x13, 0x04, true },
- { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
- { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2e, 0x4f, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2e, 0x41, true },
{ "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
{ "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
- { "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
- { "CPU_CLK_UNHALTED.REF", 0x3C, 0x01, true },
+ { "CPU_CLK_UNHALTED.CORE_P", 0x3c, 0x00, true },
+ { "CPU_CLK_UNHALTED.REF", 0x3c, 0x01, true },
{ "DL1.DIRTY_EVICTION", 0x51, 0x01, true },
{ "ICACHE.HIT", 0x80, 0x01, true },
{ "ICACHE.MISSES", 0x80, 0x02, true },
@@ -243,66 +244,66 @@ static struct name_to_event intel_goldmo
{ "FETCH_STALL.ALL", 0x86, 0x00, true },
{ "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", 0x86, 0x01, true },
{ "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", 0x86, 0x02, true },
- { "UOPS_NOT_DELIVERED.ANY", 0x9C, 0x00, true },
- { "OFFCORE_RESPONSE.0", 0xB7, 0x01, true },
- { "OFFCORE_RESPONSE.1", 0xB7, 0x02, true },
- { "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
- { "UOPS_RETIRED.ANY", 0xC2, 0x00, true },
- { "UOPS_RETIRED.MS", 0xC2, 0x01, true },
- { "UOPS_RETIRED.FPDIV", 0xC2, 0x08, true },
- { "UOPS_RETIRED.IDIV", 0xC2, 0x10, true },
- { "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
- { "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
- { "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
- { "MACHINE_CLEARS.DISAMBIGUATION", 0xC3, 0x08, true },
- { "MACHINE_CLEARS.ALL", 0xC3, 0x00, true },
- { "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
- { "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
- { "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", 0xC4, 0x80, true },
- { "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
- { "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
- { "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
- { "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
- { "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
- { "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
- { "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
- { "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
- { "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
- { "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
- { "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
- { "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
- { "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
- { "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", 0xCA, 0x01, true },
- { "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", 0xCA, 0x02, true },
- { "ISSUE_SLOTS_NOT_CONSUMED.ANY", 0xCA, 0x00, true },
- { "HW_INTERRUPTS.RECEIVED", 0xCB, 0x01, true },
- { "HW_INTERRUPTS.MASKED", 0xCB, 0x02, true },
- { "HW_INTERRUPTS.PENDING_AND_MASKED", 0xCB, 0x04, true },
- { "CYCLES_DIV_BUSY.ALL", 0xCD, 0x00, true },
- { "CYCLES_DIV_BUSY.IDIV", 0xCD, 0x01, true },
- { "CYCLES_DIV_BUSY.FPDIV", 0xCD, 0x02, true },
- { "MEM_UOPS_RETIRED.ALL_LOADS", 0xD0, 0x81, true },
- { "MEM_UOPS_RETIRED.ALL_STORES", 0xD0, 0x82, true },
- { "MEM_UOPS_RETIRED.ALL", 0xD0, 0x83, true },
- { "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0xD0, 0x11, true },
- { "MEM_UOPS_RETIRED.DTLB_MISS_STORES", 0xD0, 0x12, true },
- { "MEM_UOPS_RETIRED.DTLB_MISS", 0xD0, 0x13, true },
- { "MEM_UOPS_RETIRED.LOCK_LOADS", 0xD0, 0x21, true },
- { "MEM_UOPS_RETIRED.SPLIT_LOADS", 0xD0, 0x41, true },
- { "MEM_UOPS_RETIRED.SPLIT_STORES", 0xD0, 0x42, true },
- { "MEM_UOPS_RETIRED.SPLIT", 0xD0, 0x43, true },
- { "MEM_LOAD_UOPS_RETIRED.L1_HIT", 0xD1, 0x01, true },
- { "MEM_LOAD_UOPS_RETIRED.L1_MISS", 0xD1, 0x08, true },
- { "MEM_LOAD_UOPS_RETIRED.L2_HIT", 0xD1, 0x02, true },
- { "MEM_LOAD_UOPS_RETIRED.L2_MISS", 0xD1, 0x10, true },
- { "MEM_LOAD_UOPS_RETIRED.HITM", 0xD1, 0x20, true },
- { "MEM_LOAD_UOPS_RETIRED.WCB_HIT", 0xD1, 0x40, true },
- { "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 0xD1, 0x80, true },
- { "BACLEARS.ALL", 0xE6, 0x01, true },
- { "BACLEARS.RETURN", 0xE6, 0x08, true },
- { "BACLEAR.CONDS", 0xE6, 0x10, true },
- { "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
- { "DECODED_RESTRICTION.PREDECODE_WRONG", 0xE9, 0x01, true },
+ { "UOPS_NOT_DELIVERED.ANY", 0x9c, 0x00, true },
+ { "OFFCORE_RESPONSE.0", 0xb7, 0x01, true },
+ { "OFFCORE_RESPONSE.1", 0xb7, 0x02, true },
+ { "INST_RETIRED.ANY_P", 0xc0, 0x00, true },
+ { "UOPS_RETIRED.ANY", 0xc2, 0x00, true },
+ { "UOPS_RETIRED.MS", 0xc2, 0x01, true },
+ { "UOPS_RETIRED.FPDIV", 0xc2, 0x08, true },
+ { "UOPS_RETIRED.IDIV", 0xc2, 0x10, true },
+ { "MACHINE_CLEARS.SMC", 0xc3, 0x01, true },
+ { "MACHINE_CLEARS.MEMORY_ORDERING", 0xc3, 0x02, true },
+ { "MACHINE_CLEARS.FP_ASSIST", 0xc3, 0x04, true },
+ { "MACHINE_CLEARS.DISAMBIGUATION", 0xc3, 0x08, true },
+ { "MACHINE_CLEARS.ALL", 0xc3, 0x00, true },
+ { "BR_INST_RETIRED.ALL_BRANCHES", 0xc4, 0x00, true },
+ { "BR_INST_RETIRED.JCC", 0xc4, 0x7e, true },
+ { "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", 0xc4, 0x80, true },
+ { "BR_INST_RETIRED.TAKEN_JCC", 0xc4, 0xfe, true },
+ { "BR_INST_RETIRED.CALL", 0xc4, 0xf9, true },
+ { "BR_INST_RETIRED.REL_CALL", 0xc4, 0xfd, true },
+ { "BR_INST_RETIRED.IND_CALL", 0xc4, 0xfb, true },
+ { "BR_INST_RETIRED.RETURN", 0xc4, 0xf7, true },
+ { "BR_INST_RETIRED.NON_RETURN_IND", 0xc4, 0xeb, true },
+ { "BR_INST_RETIRED.FAR_BRANCH", 0xc4, 0xbf, true },
+ { "BR_MISP_RETIRED.ALL_BRANCHES", 0xc5, 0x00, true },
+ { "BR_MISP_RETIRED.JCC", 0xc5, 0x7e, true },
+ { "BR_MISP_RETIRED.TAKEN_JCC", 0xc5, 0xfe, true },
+ { "BR_MISP_RETIRED.IND_CALL", 0xc5, 0xfb, true },
+ { "BR_MISP_RETIRED.RETURN", 0xc5, 0xf7, true },
+ { "BR_MISP_RETIRED.NON_RETURN_IND", 0xc5, 0xeb, true },
+ { "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", 0xca, 0x01, true },
+ { "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", 0xca, 0x02, true },
+ { "ISSUE_SLOTS_NOT_CONSUMED.ANY", 0xca, 0x00, true },
+ { "HW_INTERRUPTS.RECEIVED", 0xcb, 0x01, true },
+ { "HW_INTERRUPTS.MASKED", 0xcb, 0x02, true },
+ { "HW_INTERRUPTS.PENDING_AND_MASKED", 0xcb, 0x04, true },
+ { "CYCLES_DIV_BUSY.ALL", 0xcd, 0x00, true },
+ { "CYCLES_DIV_BUSY.IDIV", 0xcd, 0x01, true },
+ { "CYCLES_DIV_BUSY.FPDIV", 0xcd, 0x02, true },
+ { "MEM_UOPS_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
+ { "MEM_UOPS_RETIRED.ALL_STORES", 0xd0, 0x82, true },
+ { "MEM_UOPS_RETIRED.ALL", 0xd0, 0x83, true },
+ { "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0xd0, 0x11, true },
+ { "MEM_UOPS_RETIRED.DTLB_MISS_STORES", 0xd0, 0x12, true },
+ { "MEM_UOPS_RETIRED.DTLB_MISS", 0xd0, 0x13, true },
+ { "MEM_UOPS_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
+ { "MEM_UOPS_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
+ { "MEM_UOPS_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
+ { "MEM_UOPS_RETIRED.SPLIT", 0xd0, 0x43, true },
+ { "MEM_LOAD_UOPS_RETIRED.L1_HIT", 0xd1, 0x01, true },
+ { "MEM_LOAD_UOPS_RETIRED.L1_MISS", 0xd1, 0x08, true },
+ { "MEM_LOAD_UOPS_RETIRED.L2_HIT", 0xd1, 0x02, true },
+ { "MEM_LOAD_UOPS_RETIRED.L2_MISS", 0xd1, 0x10, true },
+ { "MEM_LOAD_UOPS_RETIRED.HITM", 0xd1, 0x20, true },
+ { "MEM_LOAD_UOPS_RETIRED.WCB_HIT", 0xd1, 0x40, true },
+ { "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 0xd1, 0x80, true },
+ { "BACLEARS.ALL", 0xe6, 0x01, true },
+ { "BACLEARS.RETURN", 0xe6, 0x08, true },
+ { "BACLEAR.CONDS", 0xe6, 0x10, true },
+ { "MS_DECODED.MS_ENTRY", 0xe7, 0x01, true },
+ { "DECODED_RESTRICTION.PREDECODE_WRONG", 0xe9, 0x01, true },
};
static struct event_table intel_goldmont = {
@@ -333,13 +334,13 @@ static struct name_to_event intel_goldmo
{ "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
{ "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", 0x49, 0x08, true },
{ "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
- { "EPT.WALK_PENDING", 0x4F, 0x10, true },
+ { "EPT.WALK_PENDING", 0x4f, 0x10, true },
{ "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x08, true },
{ "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
{ "ITLB_MISSES.WALK_COMPLETED_1GB", 0x85, 0x08, true },
{ "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
- { "TLB_FLUSHES.STLB_ANY", 0xBD, 0x20, true },
- { "MACHINE_CLEARS.PAGE_FAULT", 0xC3, 0x20, true },
+ { "TLB_FLUSHES.STLB_ANY", 0xbd, 0x20, true },
+ { "MACHINE_CLEARS.PAGE_FAULT", 0xc3, 0x20, true },
};
static struct event_table intel_goldmontplus = {
@@ -374,142 +375,143 @@ init_intel_goldmontplus(void)
*/
static struct name_to_event intel_skylake_kabylake_names[] = {
/* Event Name - Event Select - UMask */
- { "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
- { "LD_BLOCKS.NO_SR", 0x03, 0x08, true },
- { "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 0x07, 0x01, true },
- { "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 0x08, 0x08, true },
- { "DTLB_LOAD_MISSES.WALK_COMPLETED", 0x08, 0x0E, true },
- { "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
- { "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
- { "INT_MISC.RECOVERY_CYCLES", 0x0D, 0x01, true },
- { "INT_MISC.CLEAR_RESTEER_CYCLES", 0x0D, 0x80, true },
- { "UOPS_ISSUED.ANY", 0x0E, 0x01, true },
- { "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 0x0E, 0x02, true },
- { "UOPS_ISSUED.SLOW_LEA", 0x0E, 0x20, true },
- { "L2_RQSTS.DEMAND_DATA_RD_MISS", 0x24, 0x21, true },
- { "L2_RQSTS.RFO_MISS", 0x24, 0x22, true },
- { "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
- { "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
- { "L2_RQSTS.PF_MISS", 0x24, 0x38, true },
- { "L2_RQSTS.MISS", 0x24, 0x3F, true },
- { "L2_RQSTS.DEMAND_DATA_RD_HIT", 0x24, 0x41, true },
- { "L2_RQSTS.RFO_HIT", 0x24, 0x42, true },
- { "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
- { "L2_RQSTS.PF_HIT", 0x24, 0xD8, true },
- { "L2_RQSTS.ALL_DEMAND_DATA_RD", 0x24, 0xE1, true },
- { "L2_RQSTS.ALL_RFO", 0x24, 0xE2, true },
- { "L2_RQSTS.ALL_CODE_RD", 0x24, 0xE4, true },
- { "L2_RQSTS.ALL_DEMAND_REFERENCES", 0x24, 0xE7, true },
- { "L2_RQSTS.ALL_PF", 0x24, 0xF8, true },
- { "L2_RQSTS.REFERENCES", 0x24, 0xFF, true },
- { "SW_PREFETCH_ACCESS.NTA", 0x32, 0x01, true },
- { "SW_PREFETCH_ACCESS.T0", 0x32, 0x02, true },
- { "SW_PREFETCH_ACCESS.T1_T2", 0x32, 0x04, true },
- { "SW_PREFETCH_ACCESS.PREFETCHW", 0x32, 0x08, true },
- { "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
- { "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
- { "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
- { "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
- { "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
- { "DTLB_STORE_MISSES.WALK_COMPLETED", 0x49, 0x0E, true },
- { "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
- { "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
- { "LOAD_HIT_PRE.SW_PF", 0x4C, 0x01, true },
- { "EPT.WALK_PENDING", 0x4F, 0x10, true },
- { "L1D.REPLACEMENT", 0x51, 0x01, true },
- { "RS_EVENTS.EMPTY_CYCLES", 0x5E, 0x01, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 0x60, 0x01, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 0x60, 0x02, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
- { "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 0x60, 0x10, true },
- { "IDQ.MITE_UOPS", 0x79, 0x04, true },
- { "IDQ.DSB_UOPS", 0x79, 0x08, true },
- { "IDQ.MS_MITE_UOPS", 0x79, 0x20, true },
- { "IDQ.MS_UOPS", 0x79, 0x30, true },
- { "ICACHE_16B.IFDATA_STALL", 0x80, 0x04, true },
- { "ICACHE_64B.IFTAG_HIT", 0x83, 0x01, true },
- { "ICACHE_64B.IFTAG_MISS", 0x83, 0x02, true },
- { "ICACHE_64B.IFTAG_STALL", 0x83, 0x04, true },
- { "ITLB_MISSES.MISS_CAUSES_A_WALK", 0x85, 0x01, true },
- { "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x02, true },
- { "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
- { "ITLB_MISSES.WALK_COMPLETED_1G", 0x85, 0x08, true },
- { "ITLB_MISSES.WALK_COMPLETED", 0x85, 0x0E, true },
- { "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
- { "ITLB_MISSES.STLB_HIT", 0x85, 0x20, true },
- { "ILD_STALL.LCP", 0x87, 0x01, true },
- { "IDQ_UOPS_NOT_DELIVERED.CORE", 0x9C, 0x01, true },
- { "RESOURCE_STALLS.ANY", 0xA2, 0x01, true },
- { "RESOURCE_STALLS.SB", 0xA2, 0x08, true },
- { "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 0xA6, 0x01, true },
- { "EXE_ACTIVITY.1_PORTS_UTIL", 0xA6, 0x02, true },
- { "EXE_ACTIVITY.2_PORTS_UTIL", 0xA6, 0x04, true },
- { "EXE_ACTIVITY.3_PORTS_UTIL", 0xA6, 0x08, true },
- { "EXE_ACTIVITY.4_PORTS_UTIL", 0xA6, 0x10, true },
- { "EXE_ACTIVITY.BOUND_ON_STORES", 0xA6, 0x40, true },
- { "LSD.UOPS", 0xA8, 0x01, true },
- { "DSB2MITE_SWITCHES.PENALTY_CYCLES", 0xAB, 0x02, true },
- { "ITLB.ITLB_FLUSH", 0xAE, 0x01, true },
- { "OFFCORE_REQUESTS.DEMAND_DATA_RD", 0xB0, 0x01, true },
- { "OFFCORE_REQUESTS.DEMAND_CODE_RD", 0xB0, 0x02, true },
- { "OFFCORE_REQUESTS.DEMAND_RFO", 0xB0, 0x04, true },
- { "OFFCORE_REQUESTS.ALL_DATA_RD", 0xB0, 0x08, true },
- { "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 0xB0, 0x10, true },
- { "OFFCORE_REQUESTS.ALL_REQUESTS", 0xB0, 0x80, true },
- { "UOPS_EXECUTED.THREAD", 0xB1, 0x01, true },
- { "UOPS_EXECUTED.CORE", 0xB1, 0x02, true },
- { "UOPS_EXECUTED.X87", 0xB1, 0x10, true },
- { "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 0xB2, 0x01, true },
- { "TLB_FLUSH.DTLB_THREAD", 0xBD, 0x01, true },
- { "TLB_FLUSH.STLB_ANY", 0xBD, 0x20, true },
- { "INST_RETIRED.PREC_DIST", 0xC0, 0x01, true },
- { "OTHER_ASSISTS.ANY", 0xC1, 0x3F, true },
- { "UOPS_RETIRED.RETIRE_SLOTS", 0xC2, 0x02, true },
- { "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
- { "MACHINE_CLEARS.SMC", 0xC3, 0x04, true },
- { "BR_INST_RETIRED.CONDITIONAL", 0xC4, 0x01, true },
- { "BR_INST_RETIRED.NEAR_CALL", 0xC4, 0x02, true },
- { "BR_INST_RETIRED.NEAR_RETURN", 0xC4, 0x08, true },
- { "BR_INST_RETIRED.NOT_TAKEN", 0xC4, 0x10, true },
- { "BR_INST_RETIRED.NEAR_TAKEN", 0xC4, 0x20, true },
- { "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0x40, true },
- { "BR_MISP_RETIRED.CONDITIONAL", 0xC5, 0x01, true },
- { "BR_MISP_RETIRED.NEAR_CALL", 0xC5, 0x02, true },
- { "BR_MISP_RETIRED.NEAR_TAKEN", 0xC5, 0x20, true },
- { "HW_INTERRUPTS.RECEIVED", 0xCB, 0x01, true },
- { "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xD0, 0x11, true },
- { "MEM_INST_RETIRED.STLB_MISS_STORES", 0xD0, 0x12, true },
- { "MEM_INST_RETIRED.LOCK_LOADS", 0xD0, 0x21, true },
- { "MEM_INST_RETIRED.SPLIT_LOADS", 0xD0, 0x41, true },
- { "MEM_INST_RETIRED.SPLIT_STORES", 0xD0, 0x42, true },
- { "MEM_INST_RETIRED.ALL_LOADS", 0xD0, 0x81, true },
- { "MEM_INST_RETIRED.ALL_STORES", 0xD0, 0x82, true },
- { "MEM_LOAD_RETIRED.L1_HIT", 0xD1, 0x01, true },
- { "MEM_LOAD_RETIRED.L2_HIT", 0xD1, 0x02, true },
- { "MEM_LOAD_RETIRED.L3_HIT", 0xD1, 0x04, true },
- { "MEM_LOAD_RETIRED.L1_MISS", 0xD1, 0x08, true },
- { "MEM_LOAD_RETIRED.L2_MISS", 0xD1, 0x10, true },
- { "MEM_LOAD_RETIRED.L3_MISS", 0xD1, 0x20, true },
- { "MEM_LOAD_RETIRED.FB_HIT", 0xD1, 0x40, true },
- { "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 0xD2, 0x01, true },
- { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 0xD2, 0x02, true },
- { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 0xD2, 0x04, true },
- { "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 0xD2, 0x08, true },
- { "MEM_LOAD_MISC_RETIRED.UC", 0xD4, 0x04, true },
- { "BACLEARS.ANY", 0xE6, 0x01, true },
- { "L2_TRANS.L2_WB", 0xF0, 0x40, true },
- { "L2_LINES_IN.ALL", 0xF1, 0x1F, true },
- { "L2_LINES_OUT.SILENT", 0xF2, 0x01, true },
- { "L2_LINES_OUT.NON_SILENT", 0xF2, 0x02, true },
- { "L2_LINES_OUT.USELESS_HWPF", 0xF2, 0x04, true },
- { "SQ_MISC.SPLIT_LOCK", 0xF4, 0x10, true },
+ { "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
+ { "LD_BLOCKS.NO_SR", 0x03, 0x08, true },
+ { "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 0x07, 0x01, true },
+ { "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 0x08, 0x08, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED", 0x08, 0x0e, true },
+ { "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
+ { "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
+ { "INT_MISC.RECOVERY_CYCLES", 0x0d, 0x01, true },
+ { "INT_MISC.CLEAR_RESTEER_CYCLES", 0x0d, 0x80, true },
+ { "UOPS_ISSUED.ANY", 0x0e, 0x01, true },
+ { "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 0x0e, 0x02, true },
+ { "UOPS_ISSUED.SLOW_LEA", 0x0e, 0x20, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_MISS", 0x24, 0x21, true },
+ { "L2_RQSTS.RFO_MISS", 0x24, 0x22, true },
+ { "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
+ { "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
+ { "L2_RQSTS.PF_MISS", 0x24, 0x38, true },
+ { "L2_RQSTS.MISS", 0x24, 0x3f, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_HIT", 0x24, 0x41, true },
+ { "L2_RQSTS.RFO_HIT", 0x24, 0x42, true },
+ { "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
+ { "L2_RQSTS.PF_HIT", 0x24, 0xd8, true },
+ { "L2_RQSTS.ALL_DEMAND_DATA_RD", 0x24, 0xe1, true },
+ { "L2_RQSTS.ALL_RFO", 0x24, 0xe2, true },
+ { "L2_RQSTS.ALL_CODE_RD", 0x24, 0xe4, true },
+ { "L2_RQSTS.ALL_DEMAND_REFERENCES", 0x24, 0xe7, true },
+ { "L2_RQSTS.ALL_PF", 0x24, 0xf8, true },
+ { "L2_RQSTS.REFERENCES", 0x24, 0xff, true },
+ { "SW_PREFETCH_ACCESS.NTA", 0x32, 0x01, true },
+ { "SW_PREFETCH_ACCESS.T0", 0x32, 0x02, true },
+ { "SW_PREFETCH_ACCESS.T1_T2", 0x32, 0x04, true },
+ { "SW_PREFETCH_ACCESS.PREFETCHW", 0x32, 0x08, true },
+ { "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3c, 0x02, true },
+ { "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 0x3c, 0x02, true },
+ { "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
+ { "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
+ { "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED", 0x49, 0x0e, true },
+ { "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
+ { "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
+ { "LOAD_HIT_PRE.SW_PF", 0x4c, 0x01, true },
+ { "EPT.WALK_PENDING", 0x4f, 0x10, true },
+ { "L1D.REPLACEMENT", 0x51, 0x01, true },
+ { "RS_EVENTS.EMPTY_CYCLES", 0x5e, 0x01, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 0x60, 0x01, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 0x60, 0x02, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
+ 0x60, 0x10, true },
+ { "IDQ.MITE_UOPS", 0x79, 0x04, true },
+ { "IDQ.DSB_UOPS", 0x79, 0x08, true },
+ { "IDQ.MS_MITE_UOPS", 0x79, 0x20, true },
+ { "IDQ.MS_UOPS", 0x79, 0x30, true },
+ { "ICACHE_16B.IFDATA_STALL", 0x80, 0x04, true },
+ { "ICACHE_64B.IFTAG_HIT", 0x83, 0x01, true },
+ { "ICACHE_64B.IFTAG_MISS", 0x83, 0x02, true },
+ { "ICACHE_64B.IFTAG_STALL", 0x83, 0x04, true },
+ { "ITLB_MISSES.MISS_CAUSES_A_WALK", 0x85, 0x01, true },
+ { "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x02, true },
+ { "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
+ { "ITLB_MISSES.WALK_COMPLETED_1G", 0x85, 0x08, true },
+ { "ITLB_MISSES.WALK_COMPLETED", 0x85, 0x0e, true },
+ { "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
+ { "ITLB_MISSES.STLB_HIT", 0x85, 0x20, true },
+ { "ILD_STALL.LCP", 0x87, 0x01, true },
+ { "IDQ_UOPS_NOT_DELIVERED.CORE", 0x9c, 0x01, true },
+ { "RESOURCE_STALLS.ANY", 0xa2, 0x01, true },
+ { "RESOURCE_STALLS.SB", 0xa2, 0x08, true },
+ { "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 0xa6, 0x01, true },
+ { "EXE_ACTIVITY.1_PORTS_UTIL", 0xa6, 0x02, true },
+ { "EXE_ACTIVITY.2_PORTS_UTIL", 0xa6, 0x04, true },
+ { "EXE_ACTIVITY.3_PORTS_UTIL", 0xa6, 0x08, true },
+ { "EXE_ACTIVITY.4_PORTS_UTIL", 0xa6, 0x10, true },
+ { "EXE_ACTIVITY.BOUND_ON_STORES", 0xa6, 0x40, true },
+ { "LSD.UOPS", 0xa8, 0x01, true },
+ { "DSB2MITE_SWITCHES.PENALTY_CYCLES", 0xab, 0x02, true },
+ { "ITLB.ITLB_FLUSH", 0xae, 0x01, true },
+ { "OFFCORE_REQUESTS.DEMAND_DATA_RD", 0xb0, 0x01, true },
+ { "OFFCORE_REQUESTS.DEMAND_CODE_RD", 0xb0, 0x02, true },
+ { "OFFCORE_REQUESTS.DEMAND_RFO", 0xb0, 0x04, true },
+ { "OFFCORE_REQUESTS.ALL_DATA_RD", 0xb0, 0x08, true },
+ { "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 0xb0, 0x10, true },
+ { "OFFCORE_REQUESTS.ALL_REQUESTS", 0xb0, 0x80, true },
+ { "UOPS_EXECUTED.THREAD", 0xb1, 0x01, true },
+ { "UOPS_EXECUTED.CORE", 0xb1, 0x02, true },
+ { "UOPS_EXECUTED.X87", 0xb1, 0x10, true },
+ { "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 0xb2, 0x01, true },
+ { "TLB_FLUSH.DTLB_THREAD", 0xbd, 0x01, true },
+ { "TLB_FLUSH.STLB_ANY", 0xbd, 0x20, true },
+ { "INST_RETIRED.PREC_DIST", 0xc0, 0x01, true },
+ { "OTHER_ASSISTS.ANY", 0xc1, 0x3f, true },
+ { "UOPS_RETIRED.RETIRE_SLOTS", 0xc2, 0x02, true },
+ { "MACHINE_CLEARS.MEMORY_ORDERING", 0xc3, 0x02, true },
+ { "MACHINE_CLEARS.SMC", 0xc3, 0x04, true },
+ { "BR_INST_RETIRED.CONDITIONAL", 0xc4, 0x01, true },
+ { "BR_INST_RETIRED.NEAR_CALL", 0xc4, 0x02, true },
+ { "BR_INST_RETIRED.NEAR_RETURN", 0xc4, 0x08, true },
+ { "BR_INST_RETIRED.NOT_TAKEN", 0xc4, 0x10, true },
+ { "BR_INST_RETIRED.NEAR_TAKEN", 0xc4, 0x20, true },
+ { "BR_INST_RETIRED.FAR_BRANCH", 0xc4, 0x40, true },
+ { "BR_MISP_RETIRED.CONDITIONAL", 0xc5, 0x01, true },
+ { "BR_MISP_RETIRED.NEAR_CALL", 0xc5, 0x02, true },
+ { "BR_MISP_RETIRED.NEAR_TAKEN", 0xc5, 0x20, true },
+ { "HW_INTERRUPTS.RECEIVED", 0xcb, 0x01, true },
+ { "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xd0, 0x11, true },
+ { "MEM_INST_RETIRED.STLB_MISS_STORES", 0xd0, 0x12, true },
+ { "MEM_INST_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
+ { "MEM_INST_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
+ { "MEM_INST_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
+ { "MEM_INST_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
+ { "MEM_INST_RETIRED.ALL_STORES", 0xd0, 0x82, true },
+ { "MEM_LOAD_RETIRED.L1_HIT", 0xd1, 0x01, true },
+ { "MEM_LOAD_RETIRED.L2_HIT", 0xd1, 0x02, true },
+ { "MEM_LOAD_RETIRED.L3_HIT", 0xd1, 0x04, true },
+ { "MEM_LOAD_RETIRED.L1_MISS", 0xd1, 0x08, true },
+ { "MEM_LOAD_RETIRED.L2_MISS", 0xd1, 0x10, true },
+ { "MEM_LOAD_RETIRED.L3_MISS", 0xd1, 0x20, true },
+ { "MEM_LOAD_RETIRED.FB_HIT", 0xd1, 0x40, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 0xd2, 0x01, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 0xd2, 0x02, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 0xd2, 0x04, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 0xd2, 0x08, true },
+ { "MEM_LOAD_MISC_RETIRED.UC", 0xd4, 0x04, true },
+ { "BACLEARS.ANY", 0xe6, 0x01, true },
+ { "L2_TRANS.L2_WB", 0xf0, 0x40, true },
+ { "L2_LINES_IN.ALL", 0xf1, 0x1f, true },
+ { "L2_LINES_OUT.SILENT", 0xf2, 0x01, true },
+ { "L2_LINES_OUT.NON_SILENT", 0xf2, 0x02, true },
+ { "L2_LINES_OUT.USELESS_HWPF", 0xf2, 0x04, true },
+ { "SQ_MISC.SPLIT_LOCK", 0xf4, 0x10, true },
};
static struct event_table intel_skylake_kabylake = {
@@ -523,14 +525,280 @@ static struct event_table intel_skylake_
static struct event_table *
init_intel_skylake_kabylake(void)
{
+
return &intel_skylake_kabylake;
}
+/*
+ * Intel Skylake-X (and Cascade Lake).
+ */
+static struct name_to_event intel_skylake_x_names[] = {
+ { "INST_RETIRED.ANY", 0x00, 0x01, true },
+ { "CPU_CLK_UNHALTED.THREAD", 0x00, 0x02, true },
+ { "CPU_CLK_UNHALTED.REF_TSC", 0x00, 0x03, true },
+ { "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
+ { "LD_BLOCKS.NO_SR", 0x03, 0x08, true },
+ { "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 0x07, 0x01, true },
+ { "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 0x08, 0x08, true },
+ { "DTLB_LOAD_MISSES.WALK_COMPLETED", 0x08, 0x0E, true },
+ { "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
+ { "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
+ { "INT_MISC.RECOVERY_CYCLES", 0x0D, 0x01, true },
+ { "INT_MISC.CLEAR_RESTEER_CYCLES", 0x0D, 0x80, true },
+ { "UOPS_ISSUED.ANY", 0x0E, 0x01, true },
+ { "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 0x0E, 0x02, true },
+ { "UOPS_ISSUED.SLOW_LEA", 0x0E, 0x20, true },
+ { "ARITH.DIVIDER_ACTIVE", 0x14, 0x01, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_MISS", 0x24, 0x21, true },
+ { "L2_RQSTS.RFO_MISS", 0x24, 0x22, true },
+ { "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
+ { "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
+ { "L2_RQSTS.PF_MISS", 0x24, 0x38, true },
+ { "L2_RQSTS.MISS", 0x24, 0x3F, true },
+ { "L2_RQSTS.DEMAND_DATA_RD_HIT", 0x24, 0x41, true },
+ { "L2_RQSTS.RFO_HIT", 0x24, 0x42, true },
+ { "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
+ { "L2_RQSTS.PF_HIT", 0x24, 0xD8, true },
+ { "L2_RQSTS.ALL_DEMAND_DATA_RD", 0x24, 0xE1, true },
+ { "L2_RQSTS.ALL_RFO", 0x24, 0xE2, true },
+ { "L2_RQSTS.ALL_CODE_RD", 0x24, 0xE4, true },
+ { "L2_RQSTS.ALL_DEMAND_REFERENCES", 0x24, 0xE7, true },
+ { "L2_RQSTS.ALL_PF", 0x24, 0xF8, true },
+ { "L2_RQSTS.REFERENCES All L2", 0x24, 0xFF, true },
+ { "CORE_POWER.LVL0_TURBO_LICENSE", 0x28, 0x07, true },
+ { "CORE_POWER.LVL1_TURBO_LICENSE", 0x28, 0x18, true },
+ { "CORE_POWER.LVL2_TURBO_LICENSE", 0x28, 0x20, true },
+ { "CORE_POWER.THROTTLE", 0x28, 0x40, true },
+ { "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
+ { "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
+ { "CPU_CLK_UNHALTED.THREAD_P", 0x3C, 0x00, true },
+ { "CPU_CLK_THREAD_UNHALTED.REF_XCLK", 0x3C, 0x01, true },
+ { "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
+ { "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
+ { "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
+ { "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
+ { "DTLB_STORE_MISSES.WALK_COMPLETED", 0x49, 0x0E, true },
+ { "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
+ { "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
+ { "LOAD_HIT_PRE.SW_PF", 0x4C, 0x01, true },
+ { "EPT.WALK_PENDING", 0x4F, 0x10, true },
+ { "L1D.REPLACEMENT", 0x51, 0x01, true },
+ { "TX_MEM.ABORT_CONFLICT", 0x54, 0x01, true },
+ { "TX_MEM.ABORT_CAPACITY", 0x54, 0x02, true },
+ { "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 0x54, 0x04, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 0x54, 0x08, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 0x54, 0x10, true },
+ { "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
+ 0x54, 0x20, true },
+ { "TX_MEM.HLE_ELISION_BUFFER_FULL", 0x54, 0x40, true },
+ { "TX_EXEC.MISC1", 0x5D, 0x01, true },
+ { "TX_EXEC.MISC2", 0x5D, 0x02, true },
+ { "TX_EXEC.MISC3", 0x5D, 0x04, true },
+ { "TX_EXEC.MISC4", 0x5D, 0x08, true },
+ { "TX_EXEC.MISC5", 0x5D, 0x10, true },
+ { "RS_EVENTS.EMPTY_CYCLES", 0x5E, 0x01, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+ 0x60, 0x01, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+ 0x60, 0x02, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
+ { "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
+ 0x60, 0x10, true },
+ { "IDQ.MITE_UOPS", 0x79, 0x04, true },
+ { "IDQ.DSB_UOPS", 0x79, 0x08, true },
+ { "IDQ.MS_DSB_CYCLES", 0x79, 0x10, true },
+ { "IDQ.ALL_DSB_CYCLES_4_UOPS", 0x79, 0x18, true },
+ { "IDQ.MS_MITE_UOPS", 0x79, 0x20, true },
+ { "IDQ.ALL_MITE_CYCLES_4_UOPS", 0x79, 0x24, true },
+ { "IDQ.MS_CYCLES", 0x79, 0x30, true },
+ { "ICACHE_16B.IFDATA_STALL", 0x80, 0x04, true },
+ { "ICACHE_64B.IFTAG_HIT", 0x83, 0x01, true },
+ { "ICACHE_64B.IFTAG_MISS", 0x83, 0x02, true },
+ { "ICACHE_64B.IFTAG_STALL", 0x83, 0x04, true },
+ { "ITLB_MISSES.MISS_CAUSES_A_WALK", 0x85, 0x01, true },
+ { "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x02, true },
+ { "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
+ { "ITLB_MISSES.WALK_COMPLETED_1G", 0x85, 0x08, true },
+ { "ITLB_MISSES.WALK_COMPLETED", 0x85, 0x0E, true },
+ { "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
+ { "ITLB_MISSES.STLB_HIT", 0x85, 0x20, true },
+ { "ILD_STALL.LCP", 0x87, 0x01, true },
+ { "IDQ_UOPS_NOT_DELIVERED.CORE", 0x9C, 0x01, true },
+ { "UOPS_DISPATCHED_PORT.PORT_0", 0xa1, 0x01, true },
+ { "UOPS_DISPATCHED_PORT.PORT_1", 0xa1, 0x02, true },
+ { "UOPS_DISPATCHED_PORT.PORT_2", 0xa1, 0x04, true },
+ { "UOPS_DISPATCHED_PORT.PORT_3", 0xa1, 0x08, true },
+ { "UOPS_DISPATCHED_PORT.PORT_4", 0xa1, 0x10, true },
+ { "UOPS_DISPATCHED_PORT.PORT_5", 0xa1, 0x20, true },
+ { "UOPS_DISPATCHED_PORT.PORT_6", 0xa1, 0x40, true },
+ { "UOPS_DISPATCHED_PORT.PORT_7", 0xa1, 0x80, true },
+ { "RESOURCE_STALLS.ANY", 0xa2, 0x01, true },
+ { "RESOURCE_STALLS.SB", 0xa2, 0x08, true },
+ { "CYCLE_ACTIVITY.CYCLES_L2_MISS", 0xa3, 0x01, true },
+ { "CYCLE_ACTIVITY.CYCLES_L3_MISS", 0xa3, 0x02, true },
+ { "CYCLE_ACTIVITY.STALLS_TOTAL", 0xa3, 0x04, true },
+ { "CYCLE_ACTIVITY.STALLS_L2_MISS", 0xa3, 0x05, true },
+ { "CYCLE_ACTIVITY.STALLS_L3_MISS", 0xa3, 0x06, true },
+ { "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 0xa3, 0x08, true },
+ { "CYCLE_ACTIVITY.STALLS_L1D_MISS", 0xa3, 0x0C, true },
+ { "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 0xa3, 0x10, true },
+ { "CYCLE_ACTIVITY.STALLS_MEM_ANY", 0xa3, 0x14, true },
+ { "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 0xa6, 0x01, true },
+ { "EXE_ACTIVITY.1_PORTS_UTIL", 0xa6, 0x02, true },
+ { "EXE_ACTIVITY.2_PORTS_UTIL", 0xa6, 0x04, true },
+ { "EXE_ACTIVITY.3_PORTS_UTIL", 0xa6, 0x08, true },
+ { "EXE_ACTIVITY.4_PORTS_UTIL", 0xa6, 0x10, true },
+ { "EXE_ACTIVITY.BOUND_ON_STORES", 0xa6, 0x40, true },
+ { "LSD.UOPS", 0xa8, 0x01, true },
+ { "DSB2MITE_SWITCHES.PENALTY_CYCLES", 0xaB, 0x02, true },
+ { "ITLB.ITLB_FLUSH", 0xaE, 0x01, true },
+ { "OFFCORE_REQUESTS.DEMAND_DATA_RD", 0xb0, 0x01, true },
+ { "OFFCORE_REQUESTS.DEMAND_CODE_RD", 0xb0, 0x02, true },
+ { "OFFCORE_REQUESTS.DEMAND_RFO", 0xb0, 0x04, true },
+ { "OFFCORE_REQUESTS.ALL_DATA_RD", 0xb0, 0x08, true },
+ { "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 0xb0, 0x10, true },
+ { "OFFCORE_REQUESTS.ALL_REQUESTS", 0xb0, 0x80, true },
+ { "UOPS_EXECUTED.THREAD", 0xb1, 0x01, true },
+ { "UOPS_EXECUTED.CORE", 0xb1, 0x02, true },
+ { "UOPS_EXECUTED.X87", 0xb1, 0x10, true },
+ { "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 0xb2, 0x01, true },
+ { "TLB_FLUSH.DTLB_THREAD", 0xbD, 0x01, true },
+ { "TLB_FLUSH.STLB_ANY", 0xbD, 0x20, true },
+ { "INST_RETIRED.ANY_P", 0xc0, 0x00, true },
+ { "INST_RETIRED.PREC_DIST", 0xc0, 0x01, true },
+ { "OTHER_ASSISTS.ANY", 0xc1, 0x3F, true },
+ { "UOPS_RETIRED.STALL_CYCLES", 0xc2, 0x01, true },
+ { "UOPS_RETIRED.RETIRE_SLOTS", 0xc2, 0x02, true },
+ { "MACHINE_CLEARS.COUNT", 0xc3, 0x01, true },
+ { "MACHINE_CLEARS.MEMORY_ORDERING", 0xc3, 0x02, true },
+ { "MACHINE_CLEARS.SMC", 0xc3, 0x04, true },
+ { "BR_INST_RETIRED.ALL_BRANCHES", 0xc4, 0x00, true },
+ { "BR_INST_RETIRED.CONDITIONAL", 0xc4, 0x01, true },
+ { "BR_INST_RETIRED.NEAR_CALL", 0xc4, 0x02, true },
+ { "BR_INST_RETIRED.NEAR_RETURN", 0xc4, 0x08, true },
+ { "BR_INST_RETIRED.NOT_TAKEN", 0xc4, 0x10, true },
+ { "BR_INST_RETIRED.NEAR_TAKEN", 0xc4, 0x20, true },
+ { "BR_INST_RETIRED.FAR_BRANCH", 0xc4, 0x40, true },
+ { "BR_MISP_RETIRED.ALL_BRANCHES", 0xc5, 0x00, true },
+ { "BR_MISP_RETIRED.CONDITIONAL", 0xc5, 0x01, true },
+ { "BR_MISP_RETIRED.NEAR_CALL", 0xc5, 0x02, true },
+ { "BR_MISP_RETIRED.NEAR_TAKEN", 0xc5, 0x20, true },
+ { "FRONTEND_RETIRED.DSB_MISS", 0xc6, 0x01, true },
+ { "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 0xc7, 0x01, true },
+ { "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 0xc7, 0x02, true },
+ { "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 0xc7, 0x04, true },
+ { "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 0xc7, 0x08, true },
+ { "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 0xc7, 0x10, true },
+ { "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 0xc7, 0x20, true },
+ { "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 0xc7, 0x40, true },
+ { "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 0xc7, 0x80, true },
+ { "HLE_RETIRED.START", 0xc8, 0x01, true },
+ { "HLE_RETIRED.COMMIT", 0xc8, 0x02, true },
+ { "HLE_RETIRED.ABORTED", 0xc8, 0x04, true },
+ { "HLE_RETIRED.ABORTED_MEM", 0xc8, 0x08, true },
+ { "HLE_RETIRED.ABORTED_TIMER", 0xc8, 0x10, true },
+ { "HLE_RETIRED.ABORTED_UNFRIENDLY", 0xc8, 0x20, true },
+ { "HLE_RETIRED.ABORTED_MEMTYPE", 0xc8, 0x40, true },
+ { "HLE_RETIRED.ABORTED_EVENTS", 0xc8, 0x80, true },
+ { "RTM_RETIRED.START", 0xc9, 0x01, true },
+ { "RTM_RETIRED.COMMIT", 0xc9, 0x02, true },
+ { "RTM_RETIRED.ABORTED", 0xc9, 0x04, true },
+ { "RTM_RETIRED.ABORTED_MEM", 0xc9, 0x08, true },
+ { "RTM_RETIRED.ABORTED_TIMER", 0xc9, 0x10, true },
+ { "RTM_RETIRED.ABORTED_UNFRIENDLY", 0xc9, 0x20, true },
+ { "RTM_RETIRED.ABORTED_MEMTYPE", 0xc9, 0x40, true },
+ { "RTM_RETIRED.ABORTED_EVENTS", 0xc9, 0x80, true },
+ { "FP_ASSIST.ANY", 0xca, 0x1e, true },
+ { "HW_INTERRUPTS.RECEIVED", 0xcb, 0x01, true },
+ { "ROB_MISC_EVENTS.LBR_INSERTS", 0xcc, 0x20, true },
+ { "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 0xcd, 0x01, true },
+ { "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xd0, 0x11, true },
+ { "MEM_INST_RETIRED.STLB_MISS_STORES", 0xd0, 0x12, true },
+ { "MEM_INST_RETIRED.LOCK_LOADS", 0xd0, 0x21, true },
+ { "MEM_INST_RETIRED.SPLIT_LOADS", 0xd0, 0x41, true },
+ { "MEM_INST_RETIRED.SPLIT_STORES", 0xd0, 0x42, true },
+ { "MEM_INST_RETIRED.ALL_LOADS", 0xd0, 0x81, true },
+ { "MEM_INST_RETIRED.ALL_STORES", 0xd0, 0x82, true },
+ { "MEM_LOAD_RETIRED.L1_HIT", 0xd1, 0x01, true },
+ { "MEM_LOAD_RETIRED.L2_HIT", 0xd1, 0x02, true },
+ { "MEM_LOAD_RETIRED.L3_HIT", 0xd1, 0x04, true },
+ { "MEM_LOAD_RETIRED.L1_MISS", 0xd1, 0x08, true },
+ { "MEM_LOAD_RETIRED.L2_MISS", 0xd1, 0x10, true },
+ { "MEM_LOAD_RETIRED.L3_MISS", 0xd1, 0x20, true },
+ { "MEM_LOAD_RETIRED.FB_HIT", 0xd1, 0x40, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 0xd2, 0x01, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 0xd2, 0x02, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 0xd2, 0x04, true },
+ { "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 0xd2, 0x08, true },
+ { "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 0xd3, 0x01, true },
+ { "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", 0xd3, 0x02, true },
+ { "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", 0xd3, 0x04, true },
+ { "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", 0xd3, 0x08, true },
+ { "MEM_LOAD_MISC_RETIRED.UC", 0xd4, 0x04, true },
+ { "BACLEARS.ANY", 0xe6, 0x01, true },
+ { "L2_TRANS.L2_WB", 0xf0, 0x40, true },
+ { "L2_LINES_IN.ALL", 0xf1, 0x1f, true },
+ { "L2_LINES_OUT.SILENT", 0xf2, 0x01, true },
+ { "L2_LINES_OUT.NON_SILENT", 0xf2, 0x02, true },
+ { "L2_LINES_OUT.USELESS_PREF", 0xf2, 0x04, true },
+ { "SQ_MISC.SPLIT_LOCK", 0xf4, 0x10, true },
+ { "IDI_MISC.WB_UPGRADE", 0xfe, 0x02, true },
+ { "IDI_MISC.WB_DOWNGRADE", 0xfe, 0x04, true },
+};
+
+static struct event_table intel_skylake_x = {
+ .tablename = "Intel Skylake-X",
+ .names = intel_skylake_x_names,
+ .nevents = sizeof(intel_skylake_x_names) /
+ sizeof(struct name_to_event),
+ .next = NULL
+};
+
+static struct event_table *
+init_intel_skylake_x(void)
+{
+
+ return &intel_skylake_x;
+}
+
+/*
+ * Intel Cascade Lake.
+ */
+static struct name_to_event intel_cascadelake_names[] = {
+ { "MEM_LOAD_RETIRED.LOCAL_PMM", 0xd1, 0x80, true },
+ { "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", 0xd3, 0x10, true },
+};
+
+static struct event_table intel_cascadelake = {
+ .tablename = "Intel Cascade Lake",
+ .names = intel_cascadelake_names,
+ .nevents = sizeof(intel_cascadelake_names) /
+ sizeof(struct name_to_event),
+ .next = NULL
+};
+
+static struct event_table *
+init_intel_cascadelake(void)
+{
+
+ intel_skylake_x.next = &intel_cascadelake;
+
+ return &intel_skylake_x;
+}
+
static struct event_table *
init_intel_generic(void)
{
unsigned int eax, ebx, ecx, edx;
struct event_table *table;
+ uint8_t stepping;
/*
* The kernel made sure the Architectural Version 1 PMCs were
@@ -551,33 +819,44 @@ init_intel_generic(void)
if (CPUID_TO_FAMILY(eax) == 6) {
switch (CPUID_TO_MODEL(eax)) {
case 0x37: /* Silvermont (Bay Trail) */
- case 0x4A: /* Silvermont (Tangier) */
- case 0x4C: /* Airmont (Braswell, Cherry Trail) */
- case 0x4D: /* Silvermont (Avoton, Rangeley) */
- case 0x5A: /* Silvermont (Anniedale) */
- case 0x5D: /* Silvermont (SoFIA) */
+ case 0x4a: /* Silvermont (Tangier) */
+ case 0x4c: /* Airmont (Braswell, Cherry Trail) */
+ case 0x4d: /* Silvermont (Avoton, Rangeley) */
+ case 0x5a: /* Silvermont (Anniedale) */
+ case 0x5d: /* Silvermont (SoFIA) */
table->next = init_intel_silvermont_airmont();
break;
- case 0x5C: /* Goldmont (Apollo Lake) */
- case 0x5F: /* Goldmont (Denverton) */
+ case 0x5c: /* Goldmont (Apollo Lake) */
+ case 0x5f: /* Goldmont (Denverton) */
table->next = init_intel_goldmont();
break;
- case 0x7A: /* Goldmont Plus (Gemini Lake) */
+ case 0x7a: /* Goldmont Plus (Gemini Lake) */
table->next = init_intel_goldmontplus();
break;
- case 0x4E: /* Skylake */
- case 0x5E: /* Skylake */
- case 0x8E: /* Kabylake */
- case 0x9E: /* Kabylake */
+ case 0x4e: /* Skylake */
+ case 0x5e: /* Skylake */
+ case 0x8e: /* Kaby Lake */
+ case 0x9e: /* Kaby Lake */
+ case 0xa5: /* Comet Lake */
+ case 0xa6: /* Comet Lake */
table->next = init_intel_skylake_kabylake();
break;
+
+ case 0x55: /* Skylake-X, Cascade Lake */
+ stepping = CPUID_TO_STEPPING(eax);
+ if (stepping <= 4)
+ table->next = init_intel_skylake_x();
+ else
+ table->next = init_intel_cascadelake();
+ break;
+
}
}
return table;
}
-/* -------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
/*
* AMD Family 10h
@@ -611,10 +890,10 @@ static struct name_to_event amd_f10h_nam
{ "l1cache-writeback-exclusive",0x44, 0x04, true },
{ "l1cache-writeback-owner", 0x44, 0x08, true },
{ "l1cache-writeback-modified", 0x44, 0x10, true },
- { "l1DTLB-hit-all", 0x4D, 0x07, true },
- { "l1DTLB-hit-4Kpage", 0x4D, 0x01, true },
- { "l1DTLB-hit-2Mpage", 0x4D, 0x02, true },
- { "l1DTLB-hit-1Gpage", 0x4D, 0x04, true },
+ { "l1DTLB-hit-all", 0x4d, 0x07, true },
+ { "l1DTLB-hit-4Kpage", 0x4d, 0x01, true },
+ { "l1DTLB-hit-2Mpage", 0x4d, 0x02, true },
+ { "l1DTLB-hit-1Gpage", 0x4d, 0x04, true },
{ "l1DTLB-miss-all", 0x45, 0x07, true },
{ "l1DTLB-miss-4Kpage", 0x45, 0x01, true },
{ "l1DTLB-miss-2Mpage", 0x45, 0x02, true },
@@ -633,26 +912,26 @@ static struct name_to_event amd_f10h_nam
{ "ins-refill-l2", 0x82, 0x00, true },
{ "ins-refill-sys", 0x83, 0x00, true },
{ "ins-fetch-stall", 0x87, 0x00, true },
- { "ins-retired", 0xC0, 0x00, true },
- { "ins-empty", 0xD0, 0x00, true },
- { "ops-retired", 0xC1, 0x00, true },
- { "branch-retired", 0xC2, 0x00, true },
- { "branch-miss-retired", 0xC3, 0x00, true },
- { "branch-taken-retired", 0xC4, 0x00, true },
- { "branch-taken-miss-retired", 0xC5, 0x00, true },
- { "branch-far-retired", 0xC6, 0x00, true },
- { "branch-resync-retired", 0xC7, 0x00, true },
- { "branch-near-retired", 0xC8, 0x00, true },
- { "branch-near-miss-retired", 0xC9, 0x00, true },
- { "branch-indirect-miss-retired", 0xCA, 0x00, true },
- { "int-hw", 0xCF, 0x00, true },
- { "int-cycles-masked", 0xCD, 0x00, true },
- { "int-cycles-masked-pending", 0xCE, 0x00, true },
- { "fpu-exceptions", 0xDB, 0x00, true },
- { "break-match0", 0xDC, 0x00, true },
- { "break-match1", 0xDD, 0x00, true },
- { "break-match2", 0xDE, 0x00, true },
- { "break-match3", 0xDF, 0x00, true },
+ { "ins-retired", 0xc0, 0x00, true },
+ { "ins-empty", 0xd0, 0x00, true },
+ { "ops-retired", 0xc1, 0x00, true },
+ { "branch-retired", 0xc2, 0x00, true },
+ { "branch-miss-retired", 0xc3, 0x00, true },
+ { "branch-taken-retired", 0xc4, 0x00, true },
+ { "branch-taken-miss-retired", 0xc5, 0x00, true },
+ { "branch-far-retired", 0xc6, 0x00, true },
+ { "branch-resync-retired", 0xc7, 0x00, true },
+ { "branch-near-retired", 0xc8, 0x00, true },
+ { "branch-near-miss-retired", 0xc9, 0x00, true },
+ { "branch-indirect-miss-retired", 0xca, 0x00, true },
+ { "int-hw", 0xcf, 0x00, true },
+ { "int-cycles-masked", 0xcd, 0x00, true },
+ { "int-cycles-masked-pending", 0xce, 0x00, true },
+ { "fpu-exceptions", 0xdb, 0x00, true },
+ { "break-match0", 0xdc, 0x00, true },
+ { "break-match1", 0xdd, 0x00, true },
+ { "break-match2", 0xde, 0x00, true },
+ { "break-match3", 0xdf, 0x00, true },
};
static struct event_table amd_f10h = {
@@ -794,31 +1073,31 @@ static struct name_to_event amd_f17h_nam
{ "IcCacheFillL2", 0x82, 0x00, true },
{ "IcCacheFillSys", 0x83, 0x00, true },
{ "IcFetchStall", 0x87, __BITS(2,0), true },
- { "IcCacheInval", 0x8C, __BITS(1,0), true },
+ { "IcCacheInval", 0x8c, __BITS(1,0), true },
{ "BpL1TlbMissL2Hit", 0x84, 0x00, true },
{ "BpL1TlbMissL2Miss", 0x85, 0x00, true },
{ "BpSnpReSync", 0x86, 0x00, true },
- { "BpL1BTBCorrect", 0x8A, 0x00, true },
- { "BpL2BTBCorrect", 0x8B, 0x00, true },
+ { "BpL1BTBCorrect", 0x8a, 0x00, true },
+ { "BpL2BTBCorrect", 0x8b, 0x00, true },
{ "BpTlbRel", 0x99, 0x00, true },
- { "ExRetInstr", 0xC0, 0x00, true },
- { "ExRetCops", 0xC1, 0x00, true },
- { "ExRetBrn", 0xC2, 0x00, true },
- { "ExRetBrnMisp", 0xC3, 0x00, true },
- { "ExRetBrnTkn", 0xC4, 0x00, true },
- { "ExRetBrnTknMisp", 0xC5, 0x00, true },
- { "ExRetBrnFar", 0xC6, 0x00, true },
- { "ExRetBrnResync", 0xC7, 0x00, true },
- { "ExRetBrnIndMisp", 0xCA, 0x00, true },
- { "ExRetNearRet", 0xC8, 0x00, true },
- { "ExRetNearRetMispred", 0xC9, 0x00, true },
- { "ExRetMmxFpInstr@X87", 0xCB, __BIT(0), true },
- { "ExRetMmxFpInstr@Mmx", 0xCB, __BIT(1), true },
- { "ExRetMmxFpInstr@Sse", 0xCB, __BIT(2), true },
- { "ExRetCond", 0xD1, 0x00, true },
- { "ExRetCondMisp", 0xD2, 0x00, true },
- { "ExDivBusy", 0xD3, 0x00, true },
- { "ExDivCount", 0xD4, 0x00, true },
+ { "ExRetInstr", 0xc0, 0x00, true },
+ { "ExRetCops", 0xc1, 0x00, true },
+ { "ExRetBrn", 0xc2, 0x00, true },
+ { "ExRetBrnMisp", 0xc3, 0x00, true },
+ { "ExRetBrnTkn", 0xc4, 0x00, true },
+ { "ExRetBrnTknMisp", 0xc5, 0x00, true },
+ { "ExRetBrnFar", 0xc6, 0x00, true },
+ { "ExRetBrnResync", 0xc7, 0x00, true },
+ { "ExRetBrnIndMisp", 0xca, 0x00, true },
+ { "ExRetNearRet", 0xc8, 0x00, true },
+ { "ExRetNearRetMispred", 0xc9, 0x00, true },
+ { "ExRetMmxFpInstr@X87", 0xcb, __BIT(0), true },
+ { "ExRetMmxFpInstr@Mmx", 0xcb, __BIT(1), true },
+ { "ExRetMmxFpInstr@Sse", 0xcb, __BIT(2), true },
+ { "ExRetCond", 0xd1, 0x00, true },
+ { "ExRetCondMisp", 0xd2, 0x00, true },
+ { "ExDivBusy", 0xd3, 0x00, true },
+ { "ExDivCount", 0xd4, 0x00, true },
};
static struct event_table amd_f17h = {
@@ -829,6 +1108,186 @@ static struct event_table amd_f17h = {
.next = NULL
};
+/*
+ * AMD Family 19h
+ * From PPR:
+ * - f19h model 01h B1 (zen3)
+ * - f19h model 11h B1 (zen4)
+ * - f19h model 21h B1 (zen3)
+ * - f19h model 51h A1 (zen3)
+ */
+static struct name_to_event amd_f19h_names[] = {
+ /* Model 1x only */
+ { "FpRetx87FpOps", 0x02, __BITS(2,0), true },
+
+ /* Only model 1x has bit 4 */
+ { "FpRetSseAvxOps", 0x03, __BITS(4,0), true },
+
+ { "FpRetiredSerOps", 0x05, __BITS(3,0), true },
+
+ /* Model 1x only */
+ { "FpOpsRetiredByWidth", 0x08, __BITS(5,0), true },
+ { "FpOpsRetiredByType", 0x0a, __BITS(7,0), true },
+ { "SseAvxOpsRetired", 0x0b, __BITS(7,0), true },
+ { "FpPackOpsRetired", 0x0c, __BITS(7,0), true },
+ { "PackedIntOpType", 0x0d, __BITS(7,0), true },
+
+ { "FpDispFaults", 0x0e, __BITS(3,0), true },
+ { "LsBadStatus2", 0x24, __BIT(1), true },
+ { "LsLocks", 0x25, __BIT(0), true },
+ { "LsRetClClush", 0x26, 0x00, true },
+ { "LsRetCpuid", 0x27, 0x00, true },
+ { "LsDispatch", 0x29, __BITS(2,0), true },
+ { "LsSmiRx", 0x2b, 0x00, true },
+ { "LsIntTaken", 0x2c, 0x00, true },
+ { "LsSTLF", 0x35, 0x00, true },
+ { "LsStCommitCancel2", 0x37, __BIT(0), true },
+ { "LsMabAlloc-ls", 0x41, 0x3f, true },
+ { "LsMabAlloc-hp", 0x41, 0x40, true },
+ { "LsMabAlloc-all", 0x41, 0x7f, true },
+ { "LsDmndFillsFromSys", 0x43, 0x5f, true },
+
+ /* Only model 1x has bit 7 */
+ { "LsAnyFillsFromSys", 0x44, 0xdf, true },
+
+ { "LsL1DTlbMiss", 0x45, __BITS(7,0), true },
+ { "LsMisalLoads-MA64", 0x47, __BIT(0), true },
+ { "LsMisalLoads-MA4K", 0x47, __BIT(1), true },
+ { "LsMisalLoads-all", 0x47, __BITS(1,0), true },
+ { "LsPrefInstrDisp", 0x4b, __BITS(2,0), true },
+ { "LsInefSwPref", 0x52, __BITS(1,0), true },
+
+ /* Only model 1x has bit 7 */
+ { "LsSwPfDcFills", 0x59, 0xdf, true },
+ { "LsHwPfDcFills", 0x5a, 0xdf, true },
+
+ { "LsAllocMabCount", 0x5f, 0x00, true },
+ { "LsNotHaltedCyc", 0x76, 0x00, true },
+
+ /* Model 0x, 1x and 2x only */
+ { "LsTlbFlush", 0x78, 0xff, true },
+
+ /* Model 1x only */
+ { "LsNotHaltedP0Cyc", 0x120, __BIT(0), true },
+
+ { "IcCacheFillL2", 0x82, 0x00, true },
+ { "IcCacheFillSys", 0x83, 0x00, true },
+ { "BpL1TlbMissL2TlbHit", 0x84, 0x00, true },
+ { "BpL1TlbMissL2TlbMiss-IF4K", 0x85, __BIT(0), true },
+ { "BpL1TlbMissL2TlbMiss-IF2M", 0x85, __BIT(1), true },
+ { "BpL1TlbMissL2TlbMiss-IF1G", 0x85, __BIT(2), true },
+ { "BpL1TlbMissL2TlbMiss-Coalesced4K", 0x85, __BIT(3), true },
+ { "BpL1TlbMissL2TlbMiss-all", 0x85, __BITS(3,0), true },
+
+ { "BpL2BTBCorrect", 0x8b, 0x00, true },
+ { "BpDynIndPred", 0x8e, 0x00, true },
+ { "BpDeReDirect", 0x91, 0x00, true },
+ { "BpL1TlbFetchHit-IF4K", 0x94, __BIT(0), true },
+ { "BpL1TlbFetchHit-IF2M", 0x94, __BIT(1), true },
+ { "BpL1TlbFetchHit-IF1G", 0x94, __BIT(2), true },
+ { "BpL1TlbFetchHit-all", 0x94, __BITS(2,0), true },
+
+ /* Model 1x only */
+ { "ResyncsOrNcRedirects", 0x96, 0x00, true },
+
+ { "IcTagHitMiss-hit", 0x18e, 0x07, true },
+ { "IcTagHitMiss-miss", 0x18e, 0x18, true },
+ { "IcTagHitMiss-all", 0x18e, 0x1f, true },
+ { "OpCacheHitMiss-hit", 0x28f, 0x03, true },
+ { "OpCacheHitMiss-miss", 0x28f, 0x04, true },
+ { "OpCacheHitMiss-all", 0x28f, 0x07, true },
+ { "DeOpQueueEmpty", 0xa9, 0x00, true },
+
+ /*
+ * Model 0x and 1x only.
+ * Only model 1x has bit 2.
+ */
+ { "DeSrcOpDisp", 0xaa, __BITS(2,0), true },
+
+ { "DeDisOpsFromDecoder-Fp-Ibs", 0xab, 0x04, true },
+ { "DeDisOpsFromDecoder-Int-Ibs", 0xab, 0x08, true },
+
+ /* Model 0x, 2x and newer */
+ { "DeDisOpsFromDecoder-Fp-Ret", 0xab, 0x84, true },
+ { "DeDisOpsFromDecoder-Int-Ret", 0xab, 0x88, true },
+
+ { "DeDisDispatchTokenStalls1", 0xae, 0xf7, true },
+ { "DeDisDispatchTokenStalls2", 0xaf, 0x2f, true },
+
+ /* Model 1x only */
+ { "DeNoDispatchPerSolt-empty", 0x1a0, 0x01, true },
+ { "DeNoDispatchPerSolt-backend", 0x1a0, 0x1e, true },
+ { "DeNoDispatchPerSolt-otherSMT", 0x1a0, 0x60, true },
+ { "DeAdditionalResourceStalls", 0x1a2, 0x30, true },
+
+ { "ExRetInstr", 0xc0, 0x00, true },
+ { "ExRetCops", 0xc1, 0x00, true },
+ { "ExRetBrn", 0xc2, 0x00, true },
+ { "ExRetBrnMisp", 0xc3, 0x00, true },
+ { "ExRetBrnTkn", 0xc4, 0x00, true },
+ { "ExRetBrnTknMisp", 0xc5, 0x00, true },
+ { "ExRetBrnFar", 0xc6, 0x00, true },
+ { "ExRetBrnIndMisp", 0xca, 0x00, true },
+ { "ExRetNearRet", 0xc8, 0x00, true },
+ { "ExRetNearRetMispred", 0xc9, 0x00, true },
+ { "ExRetMmxFpInstr@X87", 0xcb, __BIT(0), true },
+ { "ExRetMmxFpInstr@Mmx", 0xcb, __BIT(1), true },
+ { "ExRetMmxFpInstr@Sse", 0xcb, __BIT(2), true },
+ { "ExRetIndBrchInstr", 0xcc, 0x00, true },
+ { "ExRetCond", 0xd1, 0x00, true },
+ { "ExDivBusy", 0xd3, 0x00, true },
+ { "ExDivCount", 0xd4, 0x00, true },
+
+ /* Model 1x only */
+ { "ExDivCount-LoadAndALU", 0xd6, 0x1f, true },
+ { "ExDivCount-Load", 0xd6, 0xbf, true },
+ { "ExRetUcodeInstr", 0x1c1, 0x00, true },
+ { "ExRetUcodeOps", 0x1c2, 0x00, true },
+
+ { "ExRetMsprdBrnchInstrDirMsmtch", 0x1c7, 0x00, true },
+
+ /* Model 1x only */
+ { "ExRetUncondBrnchInstrMspred", 0x1c8, 0x00, true },
+ { "ExRetUncondBrnchInstr", 0x1c8, 0x00, true },
+
+ { "ExTaggedIbsOps", 0x1cf, __BITS(2,0), true },
+ { "ExRetFusedInstr", 0x1d0, 0x00, true },
+
+ /* Only model 1x has bit 0 */
+ { "L2RequestG1", 0x60, __BITS(7,1), true },
+
+ { "L2CacheReqStart", 0x64, __BITS(7,0), true },
+ { "L2PfHitL2-L2", 0x70, __BITS(4,0), true },
+ { "L2PfHitL2-L1", 0x70, __BITS(7,5), true },
+ { "L2PfHitL2-all", 0x70, __BITS(7,0), true },
+ { "L2PfMissL2HitL3-L2", 0x71, __BITS(4,0), true },
+ { "L2PfMissL2HitL3-L1", 0x71, __BITS(7,5), true },
+ { "L2PfMIssL2HitL3-all", 0x71, __BITS(7,0), true },
+ { "L2PfMissL2L3-L2", 0x72, __BITS(4,0), true },
+ { "L2PfMissL2L3-L1", 0x72, __BITS(7,5), true },
+ { "L2PfMIssL2L3-all", 0x72, __BITS(7,0), true },
+
+ { "L3LookupState-L3Miss", 0x04, __BIT(0), true },
+ { "L3LookupState-L3Hit", 0x04, __BITS(7,1), true },
+ { "L3LookupState-all", 0x04, __BITS(7,0), true },
+
+ /* Model 0x, 2x and newer */
+ { "XiSysFillLatency", 0x90, 0x00, true },
+ { "XiCcxSdpReq1", 0x9a, 0x00, true },
+
+ /* Model 1x only */
+ { "XiSampledLatency", 0xac, 0x00, true },
+ { "XiSampledLatencyRequests", 0xad, 0x00, true },
+};
+
+static struct event_table amd_f19h = {
+ .tablename = "AMD Family 19h",
+ .names = amd_f19h_names,
+ .nevents = sizeof(amd_f19h_names) /
+ sizeof(struct name_to_event),
+ .next = NULL
+};
+
static struct event_table *
init_amd_generic(void)
{
@@ -847,16 +1306,19 @@ init_amd_generic(void)
return &amd_f15h;
case 0x17:
return &amd_f17h;
+ case 0x19:
+ return &amd_f19h;
}
return NULL;
}
-/* -------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
int
tprof_event_init(uint32_t ident)
{
+
switch (ident) {
case TPROF_IDENT_NONE:
return -1;
@@ -882,14 +1344,14 @@ recursive_event_list(struct event_table
printf("\t%s\n", table->names[i].name);
}
- if (table->next != NULL) {
+ if (table->next != NULL)
recursive_event_list(table->next);
- }
}
void
tprof_event_list(void)
{
+
recursive_event_list(cpuevents);
}
@@ -909,15 +1371,15 @@ recursive_event_lookup(struct event_tabl
}
}
- if (table->next != NULL) {
+ if (table->next != NULL)
recursive_event_lookup(table->next, name, param);
- } else {
+ else
errx(EXIT_FAILURE, "event '%s' unknown", name);
- }
}
void
tprof_event_lookup(const char *name, struct tprof_param *param)
{
+
recursive_event_lookup(cpuevents, name, param);
}
