Module Name: src
Committed By: rin
Date: Thu Aug 24 05:46:55 UTC 2023
Modified Files:
src/sys/arch/riscv/riscv: riscv_machdep.c
Log Message:
riscv: cpu_setmcontext: Do not unconditionally update tp register
Conserve tp register for _UC_CPU and update later if _UC_TLSBASE is
specified. This is what powerpc does, which also uses a general
purpose register for TLS pointer.
Found by tests/lib/libpthread/t_swapcontext:swapcontext1, which
successfully passes now.
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/riscv/riscv/riscv_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.32 src/sys/arch/riscv/riscv/riscv_machdep.c:1.33
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.32 Fri Aug 4 09:06:33 2023
+++ src/sys/arch/riscv/riscv/riscv_machdep.c Thu Aug 24 05:46:55 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: riscv_machdep.c,v 1.32 2023/08/04 09:06:33 mrg Exp $ */
+/* $NetBSD: riscv_machdep.c,v 1.33 2023/08/24 05:46:55 rin Exp $ */
/*-
* Copyright (c) 2014, 2019, 2022 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "opt_riscv_debug.h"
#include <sys/cdefs.h>
-__RCSID("$NetBSD: riscv_machdep.c,v 1.32 2023/08/04 09:06:33 mrg Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.33 2023/08/24 05:46:55 rin Exp $");
#include <sys/param.h>
@@ -302,8 +302,12 @@ cpu_setmcontext(struct lwp *l, const mco
if (error)
return error;
- /* Save register context. */
+ /*
+ * Avoid updating TLS register here.
+ */
+ const __greg_t saved_tp = tf->tf_reg[_REG_TP];
tf->tf_regs = *(const struct reg *)gr;
+ tf->tf_reg[_REG_TP] = saved_tp;
}
/* Restore the private thread context */
