Module Name: src
Committed By: andvar
Date: Thu Aug 24 14:53:02 UTC 2023
Modified Files:
src/regress/sys/uvm/pdsim: Makefile
Log Message:
s/defult/default/
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/regress/sys/uvm/pdsim/Makefile
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/regress/sys/uvm/pdsim/Makefile
diff -u src/regress/sys/uvm/pdsim/Makefile:1.2 src/regress/sys/uvm/pdsim/Makefile:1.3
--- src/regress/sys/uvm/pdsim/Makefile:1.2 Sat Oct 14 04:59:52 2006
+++ src/regress/sys/uvm/pdsim/Makefile Thu Aug 24 14:53:02 2023
@@ -1,4 +1,4 @@
-# $Id: Makefile,v 1.2 2006/10/14 04:59:52 yamt Exp $
+# $Id: Makefile,v 1.3 2023/08/24 14:53:02 andvar Exp $
CPROGS= lirs
HPROGS= lfu lru nbsd opt rand
@@ -50,7 +50,7 @@ pdsim.dbg.cpro_${_V}: pdsim.c ${PDPOL}
# clock
-CLOCK_CFLAGS.defult=
+CLOCK_CFLAGS.default=
CLOCK_CFLAGS.inact90= -DCLOCK_INACTIVEPCT=90
PDSIM_CLOCK_VARIANTS+= default
