Module Name: src Committed By: skrll Date: Mon Jan 1 13:51:56 UTC 2024
Modified Files: src/sys/arch/riscv/dev: plic_fdt.c src/sys/arch/riscv/fdt: cpu_fdt.c riscv_fdtvar.h Log Message: Perform more checks before establishing external interrupt handlers for each hart. The VisionFive2 DTS list the S7 core with status = "disabled". To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/dev/plic_fdt.c cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/fdt/cpu_fdt.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/riscv/fdt/riscv_fdtvar.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.