Module Name: src
Committed By: andvar
Date: Mon Feb 5 22:08:05 UTC 2024
Modified Files:
src/sbin/restore: tape.c
src/sys/arch/acorn32/podulebus: if_ie.c
src/sys/arch/alpha/alpha: db_interface.c genassym.cf
src/sys/arch/dreamcast/dreamcast: machdep.c
src/sys/arch/evbarm/dev: plcomreg.h
src/sys/arch/evbsh3/evbsh3: machdep.c
src/sys/arch/hpcsh/hpcsh: machdep.c
src/sys/arch/mmeye/mmeye: machdep.c
src/sys/arch/pmax/pmax: dec_3maxplus.c
src/sys/dev/ic: interwave.c tulipreg.h
src/sys/dev/pci: if_bnxreg.h
Log Message:
triple "r" typos, mainly s/interrrupt/interrupt/ in comments and one definition.
To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sbin/restore/tape.c
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/acorn32/podulebus/if_ie.c
cvs rdiff -u -r1.42 -r1.43 src/sys/arch/alpha/alpha/db_interface.c
cvs rdiff -u -r1.30 -r1.31 src/sys/arch/alpha/alpha/genassym.cf
cvs rdiff -u -r1.45 -r1.46 src/sys/arch/dreamcast/dreamcast/machdep.c
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/evbarm/dev/plcomreg.h
cvs rdiff -u -r1.76 -r1.77 src/sys/arch/evbsh3/evbsh3/machdep.c
cvs rdiff -u -r1.78 -r1.79 src/sys/arch/hpcsh/hpcsh/machdep.c
cvs rdiff -u -r1.57 -r1.58 src/sys/arch/mmeye/mmeye/machdep.c
cvs rdiff -u -r1.71 -r1.72 src/sys/arch/pmax/pmax/dec_3maxplus.c
cvs rdiff -u -r1.43 -r1.44 src/sys/dev/ic/interwave.c \
src/sys/dev/ic/tulipreg.h
cvs rdiff -u -r1.28 -r1.29 src/sys/dev/pci/if_bnxreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sbin/restore/tape.c
diff -u src/sbin/restore/tape.c:1.74 src/sbin/restore/tape.c:1.75
--- src/sbin/restore/tape.c:1.74 Mon Dec 12 16:53:30 2022
+++ src/sbin/restore/tape.c Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: tape.c,v 1.74 2022/12/12 16:53:30 chs Exp $ */
+/* $NetBSD: tape.c,v 1.75 2024/02/05 22:08:04 andvar Exp $ */
/*
* Copyright (c) 1983, 1993
@@ -39,7 +39,7 @@
#if 0
static char sccsid[] = "@(#)tape.c 8.9 (Berkeley) 5/1/95";
#else
-__RCSID("$NetBSD: tape.c,v 1.74 2022/12/12 16:53:30 chs Exp $");
+__RCSID("$NetBSD: tape.c,v 1.75 2024/02/05 22:08:04 andvar Exp $");
#endif
#endif /* not lint */
@@ -377,7 +377,7 @@ setup(void)
* Prompt user to load a new dump volume.
* "Nextvol" is the next suggested volume to use.
* This suggested volume is enforced when doing full
- * or incremental restores, but can be overrridden by
+ * or incremental restores, but can be overridden by
* the user when only extracting a subset of the files.
*/
void
Index: src/sys/arch/acorn32/podulebus/if_ie.c
diff -u src/sys/arch/acorn32/podulebus/if_ie.c:1.54 src/sys/arch/acorn32/podulebus/if_ie.c:1.55
--- src/sys/arch/acorn32/podulebus/if_ie.c:1.54 Wed Dec 20 06:13:59 2023
+++ src/sys/arch/acorn32/podulebus/if_ie.c Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: if_ie.c,v 1.54 2023/12/20 06:13:59 thorpej Exp $ */
+/* $NetBSD: if_ie.c,v 1.55 2024/02/05 22:08:04 andvar Exp $ */
/*
* Copyright (c) 1995 Melvin Tang-Richardson.
@@ -53,7 +53,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ie.c,v 1.54 2023/12/20 06:13:59 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ie.c,v 1.55 2024/02/05 22:08:04 andvar Exp $");
#define IGNORE_ETHER1_IDROM_CHECKSUM
@@ -1345,7 +1345,7 @@ ieintr(void *arg)
if (in_intr == 1)
panic ( "ie: INTERRUPT REENTERED\n" );
- /* Clear the interrrupt */
+ /* Clear the interrupt */
ie_cli (sc);
setpage(sc, IE_IBASE + IE_SCB_OFF );
Index: src/sys/arch/alpha/alpha/db_interface.c
diff -u src/sys/arch/alpha/alpha/db_interface.c:1.42 src/sys/arch/alpha/alpha/db_interface.c:1.43
--- src/sys/arch/alpha/alpha/db_interface.c:1.42 Wed Nov 22 01:58:02 2023
+++ src/sys/arch/alpha/alpha/db_interface.c Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: db_interface.c,v 1.42 2023/11/22 01:58:02 thorpej Exp $ */
+/* $NetBSD: db_interface.c,v 1.43 2024/02/05 22:08:04 andvar Exp $ */
/*
* Mach Operating System
@@ -54,7 +54,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.42 2023/11/22 01:58:02 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_interface.c,v 1.43 2024/02/05 22:08:04 andvar Exp $");
#include <sys/param.h>
#include <sys/proc.h>
@@ -220,7 +220,7 @@ ddb_trap(unsigned long a0, unsigned long
/*
* Use SWPIPL directly; we want to avoid processing
- * software interrrupts when we go back. Soft ints
+ * software interrupts when we go back. Soft ints
* will be caught later, so not to worry.
*/
psl = alpha_pal_swpipl(ALPHA_PSL_IPL_HIGH);
Index: src/sys/arch/alpha/alpha/genassym.cf
diff -u src/sys/arch/alpha/alpha/genassym.cf:1.30 src/sys/arch/alpha/alpha/genassym.cf:1.31
--- src/sys/arch/alpha/alpha/genassym.cf:1.30 Mon Jul 12 15:21:51 2021
+++ src/sys/arch/alpha/alpha/genassym.cf Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.30 2021/07/12 15:21:51 thorpej Exp $
+# $NetBSD: genassym.cf,v 1.31 2024/02/05 22:08:04 andvar Exp $
#
# Copyright (c) 1982, 1990, 1993
@@ -139,7 +139,7 @@ define ALPHA_PSL_IPL_SOFT_LO ALPHA_PSL_I
define ALPHA_PSL_IPL_SOFT_HI ALPHA_PSL_IPL_SOFT_HI
define ALPHA_PSL_IPL_HIGH ALPHA_PSL_IPL_HIGH
-# soft interrrupt definitions
+# soft interrupt definitions
define ALPHA_ALL_SOFTINTS ALPHA_ALL_SOFTINTS
# pte bits
Index: src/sys/arch/dreamcast/dreamcast/machdep.c
diff -u src/sys/arch/dreamcast/dreamcast/machdep.c:1.45 src/sys/arch/dreamcast/dreamcast/machdep.c:1.46
--- src/sys/arch/dreamcast/dreamcast/machdep.c:1.45 Mon Mar 24 20:06:31 2014
+++ src/sys/arch/dreamcast/dreamcast/machdep.c Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.45 2014/03/24 20:06:31 christos Exp $ */
+/* $NetBSD: machdep.c,v 1.46 2024/02/05 22:08:04 andvar Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2002 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.45 2014/03/24 20:06:31 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.46 2024/02/05 22:08:04 andvar Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -280,7 +280,7 @@ intc_intr(int ssr, int spc, int ssp)
ih = EVTCODE_IH(evtcode);
KDASSERT(ih->ih_func);
/*
- * On entry, all interrrupts are disabled, and exception is enabled.
+ * On entry, all interrupts are disabled, and exception is enabled.
* Enable higher level interrupt here.
*/
_cpu_intr_resume(ih->ih_level);
Index: src/sys/arch/evbarm/dev/plcomreg.h
diff -u src/sys/arch/evbarm/dev/plcomreg.h:1.8 src/sys/arch/evbarm/dev/plcomreg.h:1.9
--- src/sys/arch/evbarm/dev/plcomreg.h:1.8 Tue Apr 11 12:56:07 2023
+++ src/sys/arch/evbarm/dev/plcomreg.h Mon Feb 5 22:08:04 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: plcomreg.h,v 1.8 2023/04/11 12:56:07 riastradh Exp $ */
+/* $NetBSD: plcomreg.h,v 1.9 2024/02/05 22:08:04 andvar Exp $ */
/*-
* Copyright (c) 2001 ARM Ltd
@@ -47,7 +47,7 @@
#define PL01X_CR_LBE 0x0080 /* Loopback enable */
#define PL010_CR_RTIE 0x0040 /* Receive timeout interrupt enable */
#define PL010_CR_TIE 0x0020 /* Transmit interrupt enable */
-#define PL010_CR_RIE 0x0010 /* Receive interrrupt enable */
+#define PL010_CR_RIE 0x0010 /* Receive interrupt enable */
#define PL010_CR_MSIE 0x0008 /* Modem status interrupt enable */
#define PL01X_CR_SIRLP 0x0004 /* IrDA SIR Low power mode */
#define PL01X_CR_SIREN 0x0002 /* SIR Enable */
Index: src/sys/arch/evbsh3/evbsh3/machdep.c
diff -u src/sys/arch/evbsh3/evbsh3/machdep.c:1.76 src/sys/arch/evbsh3/evbsh3/machdep.c:1.77
--- src/sys/arch/evbsh3/evbsh3/machdep.c:1.76 Sat Jul 25 23:38:48 2020
+++ src/sys/arch/evbsh3/evbsh3/machdep.c Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.76 2020/07/25 23:38:48 uwe Exp $ */
+/* $NetBSD: machdep.c,v 1.77 2024/02/05 22:08:05 andvar Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.76 2020/07/25 23:38:48 uwe Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.77 2024/02/05 22:08:05 andvar Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -563,7 +563,7 @@ intc_intr(int ssr, int spc, int ssp)
ih = EVTCODE_IH(evtcode);
KDASSERT(ih->ih_func);
/*
- * On entry, all interrrupts are disabled,
+ * On entry, all interrupts are disabled,
* and exception is enabled for P3 access. (kernel stack is P3,
* SH3 may or may not cause TLB miss when access stack.)
* Enable higher level interrupt here.
Index: src/sys/arch/hpcsh/hpcsh/machdep.c
diff -u src/sys/arch/hpcsh/hpcsh/machdep.c:1.78 src/sys/arch/hpcsh/hpcsh/machdep.c:1.79
--- src/sys/arch/hpcsh/hpcsh/machdep.c:1.78 Mon Nov 6 03:47:46 2017
+++ src/sys/arch/hpcsh/hpcsh/machdep.c Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.78 2017/11/06 03:47:46 christos Exp $ */
+/* $NetBSD: machdep.c,v 1.79 2024/02/05 22:08:05 andvar Exp $ */
/*-
* Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.78 2017/11/06 03:47:46 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.79 2024/02/05 22:08:05 andvar Exp $");
#include "opt_md.h"
#include "opt_ddb.h"
@@ -604,7 +604,7 @@ intc_intr(int ssr, int spc, int ssp)
ih = EVTCODE_IH(evtcode);
KDASSERT(ih->ih_func);
/*
- * On entry, all interrrupts are disabled,
+ * On entry, all interrupts are disabled,
* and exception is enabled for P3 access. (kernel stack is P3,
* SH3 may or may not cause TLB miss when access stack.)
* Enable higher level interrupt here.
Index: src/sys/arch/mmeye/mmeye/machdep.c
diff -u src/sys/arch/mmeye/mmeye/machdep.c:1.57 src/sys/arch/mmeye/mmeye/machdep.c:1.58
--- src/sys/arch/mmeye/mmeye/machdep.c:1.57 Fri Nov 8 02:24:53 2013
+++ src/sys/arch/mmeye/mmeye/machdep.c Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.57 2013/11/08 02:24:53 christos Exp $ */
+/* $NetBSD: machdep.c,v 1.58 2024/02/05 22:08:05 andvar Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.57 2013/11/08 02:24:53 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.58 2024/02/05 22:08:05 andvar Exp $");
#include "opt_ddb.h"
#include "opt_memsize.h"
@@ -657,7 +657,7 @@ intc_intr(int ssr, int spc, int ssp)
ih = EVTCODE_IH(evtcode);
KDASSERT(ih->ih_func);
/*
- * On entry, all interrrupts are disabled,
+ * On entry, all interrupts are disabled,
* and exception is enabled for P3 access. (kernel stack is P3,
* SH3 may or may not cause TLB miss when access stack.)
* Enable higher level interrupt here.
Index: src/sys/arch/pmax/pmax/dec_3maxplus.c
diff -u src/sys/arch/pmax/pmax/dec_3maxplus.c:1.71 src/sys/arch/pmax/pmax/dec_3maxplus.c:1.72
--- src/sys/arch/pmax/pmax/dec_3maxplus.c:1.71 Tue Mar 22 04:48:25 2016
+++ src/sys/arch/pmax/pmax/dec_3maxplus.c Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3maxplus.c,v 1.71 2016/03/22 04:48:25 mrg Exp $ */
+/* $NetBSD: dec_3maxplus.c,v 1.72 2024/02/05 22:08:05 andvar Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -70,7 +70,7 @@
#define __INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.71 2016/03/22 04:48:25 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.72 2024/02/05 22:08:05 andvar Exp $");
#include <sys/param.h>
#include <sys/cpu.h>
@@ -85,7 +85,7 @@ __KERNEL_RCSID(0, "$NetBSD: dec_3maxplus
/* all these to get ioasic_base */
#include <dev/tc/tcvar.h> /* tc type definitions for.. */
-#include <dev/tc/ioasicreg.h> /* ioasic interrrupt masks */
+#include <dev/tc/ioasicreg.h> /* ioasic interrupt masks */
#include <dev/tc/ioasicvar.h> /* ioasic_base */
#include <pmax/sysconf.h>
Index: src/sys/dev/ic/interwave.c
diff -u src/sys/dev/ic/interwave.c:1.43 src/sys/dev/ic/interwave.c:1.44
--- src/sys/dev/ic/interwave.c:1.43 Sat Feb 29 05:51:11 2020
+++ src/sys/dev/ic/interwave.c Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: interwave.c,v 1.43 2020/02/29 05:51:11 isaki Exp $ */
+/* $NetBSD: interwave.c,v 1.44 2024/02/05 22:08:05 andvar Exp $ */
/*
* Copyright (c) 1997, 1999, 2008 The NetBSD Foundation, Inc.
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interwave.c,v 1.43 2020/02/29 05:51:11 isaki Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interwave.c,v 1.44 2024/02/05 22:08:05 andvar Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -142,7 +142,7 @@ iwintr(void *arg)
/*
* The proper order to do this seems to be to read CSR3 to get the
- * int cause and fifo over underrrun status, then deal with the ints
+ * int cause and fifo over underrun status, then deal with the ints
* (new DMA set up), and to clear ints by writing the respective bit
* to 0.
*/
Index: src/sys/dev/ic/tulipreg.h
diff -u src/sys/dev/ic/tulipreg.h:1.43 src/sys/dev/ic/tulipreg.h:1.44
--- src/sys/dev/ic/tulipreg.h:1.43 Mon Aug 1 07:37:18 2022
+++ src/sys/dev/ic/tulipreg.h Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: tulipreg.h,v 1.43 2022/08/01 07:37:18 mlelstv Exp $ */
+/* $NetBSD: tulipreg.h,v 1.44 2024/02/05 22:08:05 andvar Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -558,7 +558,7 @@ struct tulip_desc {
descriptor, write status */
#define STATUS_DM_TS_SUSPENDED 0x00700000 /* Suspended */
#define STATUS_EB 0x03800000 /* error bits */
-#define STATUS_EB_PARITY 0x00000000 /* parity errror */
+#define STATUS_EB_PARITY 0x00000000 /* parity error */
#define STATUS_EB_MABT 0x00800000 /* master abort */
#define STATUS_EB_TABT 0x01000000 /* target abort */
#define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */
Index: src/sys/dev/pci/if_bnxreg.h
diff -u src/sys/dev/pci/if_bnxreg.h:1.28 src/sys/dev/pci/if_bnxreg.h:1.29
--- src/sys/dev/pci/if_bnxreg.h:1.28 Sun Dec 12 13:05:14 2021
+++ src/sys/dev/pci/if_bnxreg.h Mon Feb 5 22:08:05 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: if_bnxreg.h,v 1.28 2021/12/12 13:05:14 andvar Exp $ */
+/* $NetBSD: if_bnxreg.h,v 1.29 2024/02/05 22:08:05 andvar Exp $ */
/* $OpenBSD: if_bnxreg.h,v 1.33 2009/09/05 16:02:28 claudio Exp $ */
/*-
@@ -3892,7 +3892,7 @@ struct l2_fhdr {
#define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
#define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
#define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
-#define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12)
+#define BNX_TXP_CPU_STATE_INTERRUPT (1L<<12)
#define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
#define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
#define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
