Module Name: src
Committed By: macallan
Date: Tue Feb 13 13:40:13 UTC 2024
Modified Files:
src/sys/arch/hppa/conf: files.hppa
Added Files:
src/sys/arch/hppa/dev: gftfb.c
Log Message:
crude beginning of a native driver for PCI Visualize EG cards
so far it supports:
- colour
- virtual consoles
todo:
- mmap
- hardware acceleration
- STI refactoring
To generate a diff of this commit:
cvs rdiff -u -r1.24 -r1.25 src/sys/arch/hppa/conf/files.hppa
cvs rdiff -u -r0 -r1.1 src/sys/arch/hppa/dev/gftfb.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/hppa/conf/files.hppa
diff -u src/sys/arch/hppa/conf/files.hppa:1.24 src/sys/arch/hppa/conf/files.hppa:1.25
--- src/sys/arch/hppa/conf/files.hppa:1.24 Wed Mar 23 17:35:41 2022
+++ src/sys/arch/hppa/conf/files.hppa Tue Feb 13 13:40:13 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.hppa,v 1.24 2022/03/23 17:35:41 macallan Exp $
+# $NetBSD: files.hppa,v 1.25 2024/02/13 13:40:13 macallan Exp $
#
# $OpenBSD: files.hppa,v 1.31 2001/06/26 02:41:25 mickey Exp $
#
@@ -271,6 +271,10 @@ file arch/hppa/gsc/com_harmony.c com_har
#attach myri at pci
#file dev/pci/myri.c myri
+# PCI Visualize EG
+device gftfb: wsemuldisplaydev, rasops8, vcons, glyphcache, sti_pci, sti
+attach gftfb at pci
+file arch/hppa/dev/gftfb.c gftfb
# Memory Disk
file dev/md_root.c memory_disk_hooks
Added files:
Index: src/sys/arch/hppa/dev/gftfb.c
diff -u /dev/null src/sys/arch/hppa/dev/gftfb.c:1.1
--- /dev/null Tue Feb 13 13:40:13 2024
+++ src/sys/arch/hppa/dev/gftfb.c Tue Feb 13 13:40:13 2024
@@ -0,0 +1,895 @@
+/* $NetBSD: gftfb.c,v 1.1 2024/02/13 13:40:13 macallan Exp $ */
+
+/* $OpenBSD: sti_pci.c,v 1.7 2009/02/06 22:51:04 miod Exp $ */
+
+/*
+ * Copyright (c) 2006, 2007 Miodrag Vallat.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice, this permission notice, and the disclaimer below
+ * appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kmem.h>
+#include <sys/device.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pciio.h>
+
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/wscons/wsconsio.h>
+#include <dev/wsfont/wsfont.h>
+#include <dev/rasops/rasops.h>
+#include <dev/wscons/wsdisplay_vconsvar.h>
+#include <dev/pci/wsdisplay_pci.h>
+#include <dev/wscons/wsdisplay_glyphcachevar.h>
+
+#include <dev/ic/stireg.h>
+#include <dev/ic/stivar.h>
+
+#ifdef STIDEBUG
+#define DPRINTF(s) do { \
+ if (stidebug) \
+ printf s; \
+} while(0)
+
+extern int stidebug;
+#else
+#define DPRINTF(s) /* */
+#endif
+
+int gftfb_match(device_t, cfdata_t, void *);
+void gftfb_attach(device_t, device_t, void *);
+
+struct gftfb_softc {
+ device_t sc_dev;
+ pci_chipset_tag_t sc_pc;
+ pcitag_t sc_tag;
+
+ /* stuff we need in order to use the STI ROM */
+ struct sti_softc sc_base;
+ struct sti_screen sc_scr;
+ bus_space_handle_t sc_romh;
+
+ int sc_width, sc_height;
+ int sc_locked;
+ struct vcons_screen sc_console_screen;
+ struct wsscreen_descr sc_defaultscreen_descr;
+ const struct wsscreen_descr *sc_screens[1];
+ struct wsscreen_list sc_screenlist;
+ struct vcons_data vd;
+ int sc_mode;
+ u_char sc_cmap_red[256];
+ u_char sc_cmap_green[256];
+ u_char sc_cmap_blue[256];
+ glyphcache sc_gc;
+};
+
+CFATTACH_DECL_NEW(gftfb, sizeof(struct gftfb_softc),
+ gftfb_match, gftfb_attach, NULL, NULL);
+
+int gftfb_readbar(struct sti_softc *, struct pci_attach_args *, u_int, int);
+int gftfb_check_rom(struct gftfb_softc *, struct pci_attach_args *);
+void gftfb_enable_rom(struct sti_softc *);
+void gftfb_disable_rom(struct sti_softc *);
+void gftfb_enable_rom_internal(struct gftfb_softc *);
+void gftfb_disable_rom_internal(struct gftfb_softc *);
+
+void gftfb_setup(struct gftfb_softc *);
+void gftfb_wait(struct gftfb_softc *);
+
+#define ngle_bt458_write(memt, memh, r, v) \
+ bus_space_write_stream_4(memt, memh, NGLE_REG_RAMDAC + ((r) << 2), (v) << 24)
+
+void gftfb_setup_fb(struct gftfb_softc *);
+
+/* XXX these really need o go into their own header */
+int sti_pci_is_console(struct pci_attach_args *, bus_addr_t *);
+int sti_rom_setup(struct sti_rom *, bus_space_tag_t, bus_space_tag_t,
+ bus_space_handle_t, bus_addr_t *, u_int);
+int sti_screen_setup(struct sti_screen *, int);
+void sti_describe_screen(struct sti_softc *, struct sti_screen *);
+
+#define PCI_ROM_SIZE(mr) \
+ (PCI_MAPREG_ROM_ADDR(mr) & -PCI_MAPREG_ROM_ADDR(mr))
+
+/* wsdisplay stuff */
+static int gftfb_ioctl(void *, void *, u_long, void *, int,
+ struct lwp *);
+static paddr_t gftfb_mmap(void *, void *, off_t, int);
+static void gftfb_init_screen(void *, struct vcons_screen *, int, long *);
+
+static int gftfb_putcmap(struct gftfb_softc *, struct wsdisplay_cmap *);
+static int gftfb_getcmap(struct gftfb_softc *, struct wsdisplay_cmap *);
+static void gftfb_restore_palette(struct gftfb_softc *);
+static int gftfb_putpalreg(struct gftfb_softc *, uint8_t, uint8_t,
+ uint8_t, uint8_t);
+
+#if 0
+static void gftfb_rectfill(struct gftfb_softc *, int, int, int, int,
+ uint32_t);
+static void gftfb_bitblt(void *, int, int, int, int, int,
+ int, int);
+
+static void gftfb_cursor(void *, int, int, int);
+static void gftfb_putchar(void *, int, int, u_int, long);
+static void gftfb_putchar_aa(void *, int, int, u_int, long);
+static void gftfb_copycols(void *, int, int, int, int);
+static void gftfb_erasecols(void *, int, int, int, long);
+static void gftfb_copyrows(void *, int, int, int);
+static void gftfb_eraserows(void *, int, int, long);
+#endif
+
+struct wsdisplay_accessops gftfb_accessops = {
+ gftfb_ioctl,
+ gftfb_mmap,
+ NULL, /* alloc_screen */
+ NULL, /* free_screen */
+ NULL, /* show_screen */
+ NULL, /* load_font */
+ NULL, /* pollc */
+ NULL /* scroll */
+};
+
+int
+gftfb_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct pci_attach_args *paa = aux;
+
+ if (PCI_VENDOR(paa->pa_id) != PCI_VENDOR_HP)
+ return 0;
+
+ if (PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_EG)
+ return 10; /* beat out sti at pci */
+
+ return 0;
+}
+
+void
+gftfb_attach(device_t parent, device_t self, void *aux)
+{
+ struct gftfb_softc *sc = device_private(self);
+ struct pci_attach_args *paa = aux;
+ struct sti_rom *rom;
+ struct rasops_info *ri;
+ struct wsemuldisplaydev_attach_args aa;
+ unsigned long defattr;
+ int ret, is_console = 0, i, j;
+ uint8_t cmap[768];
+
+ sc->sc_dev = self;
+
+ sc->sc_pc = paa->pa_pc;
+ sc->sc_tag = paa->pa_tag;
+ sc->sc_base.sc_dev = self;
+ sc->sc_base.sc_enable_rom = gftfb_enable_rom;
+ sc->sc_base.sc_disable_rom = gftfb_disable_rom;
+
+ aprint_normal("\n");
+
+ if (gftfb_check_rom(sc, paa) != 0)
+ return;
+
+ ret = sti_pci_is_console(paa, sc->sc_base. bases);
+ if (ret != 0) {
+ sc->sc_base.sc_flags |= STI_CONSOLE;
+ is_console = 1;
+ }
+ rom = (struct sti_rom *)kmem_zalloc(sizeof(*rom), KM_SLEEP);
+ rom->rom_softc = &sc->sc_base;
+ ret = sti_rom_setup(rom, paa->pa_iot, paa->pa_memt, sc->sc_romh, sc->sc_base.bases, STI_CODEBASE_MAIN);
+ if (ret != 0) {
+ kmem_free(rom, sizeof(*rom));
+ return;
+ }
+
+ sc->sc_base.sc_rom = rom;
+
+ sc->sc_scr.scr_rom = sc->sc_base.sc_rom;
+ ret = sti_screen_setup(&sc->sc_scr, STI_FBMODE);
+
+ sc->sc_width = sc->sc_scr.scr_cfg.scr_width;
+ sc->sc_height = sc->sc_scr.scr_cfg.scr_height;
+
+ aprint_normal_dev(sc->sc_dev, "%s at %dx%d\n", sc->sc_scr.name,
+ sc->sc_width, sc->sc_height);
+ gftfb_setup(sc);
+
+ sc->sc_defaultscreen_descr = (struct wsscreen_descr){
+ "default",
+ 0, 0,
+ NULL,
+ 8, 16,
+ WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE |
+ WSSCREEN_RESIZE,
+ NULL
+ };
+
+ sc->sc_screens[0] = &sc->sc_defaultscreen_descr;
+ sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens};
+ sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
+ sc->sc_locked = 0;
+
+ vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr,
+ &gftfb_accessops);
+ sc->vd.init_screen = gftfb_init_screen;
+ sc->vd.show_screen_cookie = &sc->sc_gc;
+ sc->vd.show_screen_cb = glyphcache_adapt;
+
+ ri = &sc->sc_console_screen.scr_ri;
+
+#if 0
+ sc->sc_gc.gc_bitblt = gftfb_bitblt;
+ sc->sc_gc.gc_blitcookie = sc;
+ sc->sc_gc.gc_rop = 0x0c;
+#endif
+ if (is_console) {
+ vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1,
+ &defattr);
+ sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
+
+#if 0
+ gftfb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height,
+ ri->ri_devcmap[(defattr >> 16) & 0xff]);
+#endif
+ sc->sc_defaultscreen_descr.textops = &ri->ri_ops;
+ sc->sc_defaultscreen_descr.capabilities = ri->ri_caps;
+ sc->sc_defaultscreen_descr.nrows = ri->ri_rows;
+ sc->sc_defaultscreen_descr.ncols = ri->ri_cols;
+#if 0
+ glyphcache_init(&sc->sc_gc, sc->sc_height + 5,
+ (0x800000 / sc->sc_stride) - sc->sc_height - 5,
+ sc->sc_width,
+ ri->ri_font->fontwidth,
+ ri->ri_font->fontheight,
+ defattr);
+#endif
+ wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0,
+ defattr);
+ vcons_replay_msgbuf(&sc->sc_console_screen);
+ } else {
+ /*
+ * since we're not the console we can postpone the rest
+ * until someone actually allocates a screen for us
+ */
+ if (sc->sc_console_screen.scr_ri.ri_rows == 0) {
+ /* do some minimal setup to avoid weirdnesses later */
+ vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1,
+ &defattr);
+ } else
+ (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
+#if 0
+ glyphcache_init(&sc->sc_gc, sc->sc_height + 5,
+ (0x800000 / sc->sc_stride) - sc->sc_height - 5,
+ sc->sc_width,
+ ri->ri_font->fontwidth,
+ ri->ri_font->fontheight,
+ defattr);
+#endif
+ }
+
+ j = 0;
+ rasops_get_cmap(ri, cmap, sizeof(cmap));
+ for (i = 0; i < 256; i++) {
+ sc->sc_cmap_red[i] = cmap[j];
+ sc->sc_cmap_green[i] = cmap[j + 1];
+ sc->sc_cmap_blue[i] = cmap[j + 2];
+ gftfb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]);
+ j += 3;
+ }
+
+ /* no suspend/resume support yet */
+ if (!pmf_device_register(sc->sc_dev, NULL, NULL))
+ aprint_error_dev(sc->sc_dev,
+ "couldn't establish power handler\n");
+
+ aa.console = is_console;
+ aa.scrdata = &sc->sc_screenlist;
+ aa.accessops = &gftfb_accessops;
+ aa.accesscookie = &sc->vd;
+
+ config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE);
+}
+
+/*
+ * Grovel the STI ROM image.
+ */
+int
+gftfb_check_rom(struct gftfb_softc *spc, struct pci_attach_args *pa)
+{
+ struct sti_softc *sc = &spc->sc_base;
+ pcireg_t address, mask;
+ bus_space_handle_t romh;
+ bus_size_t romsize, subsize, stiromsize;
+ bus_addr_t selected, offs, suboffs;
+ uint32_t tmp;
+ int i;
+ int rc;
+
+ /* sort of inline sti_pci_enable_rom(sc) */
+ address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
+ ~PCI_MAPREG_ROM_ENABLE);
+ mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);
+ address |= PCI_MAPREG_ROM_ENABLE;
+ pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address);
+ sc->sc_flags |= STI_ROM_ENABLED;
+ /*
+ * Map the complete ROM for now.
+ */
+
+ romsize = PCI_ROM_SIZE(mask);
+ DPRINTF(("%s: mapping rom @ %lx for %lx\n", __func__,
+ (long)PCI_MAPREG_ROM_ADDR(address), (long)romsize));
+
+ rc = bus_space_map(pa->pa_memt, PCI_MAPREG_ROM_ADDR(address), romsize,
+ 0, &romh);
+ if (rc != 0) {
+ aprint_error_dev(sc->sc_dev, "can't map PCI ROM (%d)\n", rc);
+ goto fail2;
+ }
+
+ gftfb_disable_rom_internal(spc);
+ /*
+ * Iterate over the ROM images, pick the best candidate.
+ */
+
+ selected = (bus_addr_t)-1;
+ for (offs = 0; offs < romsize; offs += subsize) {
+ gftfb_enable_rom_internal(spc);
+ /*
+ * Check for a valid ROM header.
+ */
+ tmp = bus_space_read_4(pa->pa_memt, romh, offs + 0);
+ tmp = le32toh(tmp);
+ if (tmp != 0x55aa0000) {
+ gftfb_disable_rom_internal(spc);
+ if (offs == 0) {
+ aprint_error_dev(sc->sc_dev,
+ "invalid PCI ROM header signature (%08x)\n",
+ tmp);
+ rc = EINVAL;
+ }
+ break;
+ }
+
+ /*
+ * Check ROM type.
+ */
+ tmp = bus_space_read_4(pa->pa_memt, romh, offs + 4);
+ tmp = le32toh(tmp);
+ if (tmp != 0x00000001) { /* 1 == STI ROM */
+ gftfb_disable_rom_internal(spc);
+ if (offs == 0) {
+ aprint_error_dev(sc->sc_dev,
+ "invalid PCI ROM type (%08x)\n", tmp);
+ rc = EINVAL;
+ }
+ break;
+ }
+
+ subsize = (bus_addr_t)bus_space_read_2(pa->pa_memt, romh,
+ offs + 0x0c);
+ subsize <<= 9;
+
+#ifdef STIDEBUG
+ gftfb_disable_rom_internal(spc);
+ DPRINTF(("ROM offset %08x size %08x type %08x",
+ (u_int)offs, (u_int)subsize, tmp));
+ gftfb_enable_rom_internal(spc);
+#endif
+
+ /*
+ * Check for a valid ROM data structure.
+ * We do not need it except to know what architecture the ROM
+ * code is for.
+ */
+
+ suboffs = offs +(bus_addr_t)bus_space_read_2(pa->pa_memt, romh,
+ offs + 0x18);
+ tmp = bus_space_read_4(pa->pa_memt, romh, suboffs + 0);
+ tmp = le32toh(tmp);
+ if (tmp != 0x50434952) { /* PCIR */
+ gftfb_disable_rom_internal(spc);
+ if (offs == 0) {
+ aprint_error_dev(sc->sc_dev, "invalid PCI data"
+ " signature (%08x)\n", tmp);
+ rc = EINVAL;
+ } else {
+ DPRINTF((" invalid PCI data signature %08x\n",
+ tmp));
+ continue;
+ }
+ }
+
+ tmp = bus_space_read_1(pa->pa_memt, romh, suboffs + 0x14);
+ gftfb_disable_rom_internal(spc);
+ DPRINTF((" code %02x", tmp));
+
+ switch (tmp) {
+#ifdef __hppa__
+ case 0x10:
+ if (selected == (bus_addr_t)-1)
+ selected = offs;
+ break;
+#endif
+#ifdef __i386__
+ case 0x00:
+ if (selected == (bus_addr_t)-1)
+ selected = offs;
+ break;
+#endif
+ default:
+#ifdef STIDEBUG
+ DPRINTF((" (wrong architecture)"));
+#endif
+ break;
+ }
+ DPRINTF(("%s\n", selected == offs ? " -> SELECTED" : ""));
+ }
+
+ if (selected == (bus_addr_t)-1) {
+ if (rc == 0) {
+ aprint_error_dev(sc->sc_dev, "found no ROM with "
+ "correct microcode architecture\n");
+ rc = ENOEXEC;
+ }
+ goto fail;
+ }
+
+ /*
+ * Read the STI region BAR assignments.
+ */
+
+ gftfb_enable_rom_internal(spc);
+ offs = selected +
+ (bus_addr_t)bus_space_read_2(pa->pa_memt, romh, selected + 0x0e);
+ for (i = 0; i < STI_REGION_MAX; i++) {
+ rc = gftfb_readbar(sc, pa, i,
+ bus_space_read_1(pa->pa_memt, romh, offs + i));
+ if (rc != 0)
+ goto fail;
+ }
+
+ /*
+ * Find out where the STI ROM itself lies, and its size.
+ */
+
+ offs = selected +
+ (bus_addr_t)bus_space_read_4(pa->pa_memt, romh, selected + 0x08);
+ stiromsize = (bus_addr_t)bus_space_read_4(pa->pa_memt, romh,
+ offs + 0x18);
+ stiromsize = le32toh(stiromsize);
+ gftfb_disable_rom_internal(spc);
+
+ /*
+ * Replace our mapping with a smaller mapping of only the area
+ * we are interested in.
+ */
+
+ DPRINTF(("remapping rom @ %lx for %lx\n",
+ (long)(PCI_MAPREG_ROM_ADDR(address) + offs), (long)stiromsize));
+ bus_space_unmap(pa->pa_memt, romh, romsize);
+ rc = bus_space_map(pa->pa_memt, PCI_MAPREG_ROM_ADDR(address) + offs,
+ stiromsize, 0, &spc->sc_romh);
+ if (rc != 0) {
+ aprint_error_dev(sc->sc_dev, "can't map STI ROM (%d)\n",
+ rc);
+ goto fail2;
+ }
+ gftfb_disable_rom_internal(spc);
+ sc->sc_flags &= ~STI_ROM_ENABLED;
+
+ return 0;
+
+fail:
+ bus_space_unmap(pa->pa_memt, romh, romsize);
+fail2:
+ gftfb_disable_rom_internal(spc);
+
+ return rc;
+}
+
+/*
+ * Decode a BAR register.
+ */
+int
+gftfb_readbar(struct sti_softc *sc, struct pci_attach_args *pa, u_int region,
+ int bar)
+{
+ bus_addr_t addr;
+ bus_size_t size;
+ uint32_t cf;
+ int rc;
+
+ if (bar == 0) {
+ sc->bases[region] = 0;
+ return (0);
+ }
+
+#ifdef DIAGNOSTIC
+ if (bar < PCI_MAPREG_START || bar > PCI_MAPREG_PPB_END) {
+ gftfb_disable_rom(sc);
+ printf("%s: unexpected bar %02x for region %d\n",
+ device_xname(sc->sc_dev), bar, region);
+ gftfb_enable_rom(sc);
+ }
+#endif
+
+ cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar);
+
+ rc = pci_mapreg_info(pa->pa_pc, pa->pa_tag, bar, PCI_MAPREG_TYPE(cf),
+ &addr, &size, NULL);
+
+ if (rc != 0) {
+ gftfb_disable_rom(sc);
+ aprint_error_dev(sc->sc_dev, "invalid bar %02x for region %d\n",
+ bar, region);
+ gftfb_enable_rom(sc);
+ return (rc);
+ }
+
+ sc->bases[region] = addr;
+ return (0);
+}
+
+/*
+ * Enable PCI ROM.
+ */
+void
+gftfb_enable_rom_internal(struct gftfb_softc *spc)
+{
+ pcireg_t address;
+
+ KASSERT(spc != NULL);
+
+ address = pci_conf_read(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM);
+ address |= PCI_MAPREG_ROM_ENABLE;
+ pci_conf_write(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM, address);
+}
+
+void
+gftfb_enable_rom(struct sti_softc *sc)
+{
+ struct gftfb_softc *spc = device_private(sc->sc_dev);
+
+ if (!ISSET(sc->sc_flags, STI_ROM_ENABLED)) {
+ gftfb_enable_rom_internal(spc);
+ }
+ SET(sc->sc_flags, STI_ROM_ENABLED);
+}
+
+/*
+ * Disable PCI ROM.
+ */
+void
+gftfb_disable_rom_internal(struct gftfb_softc *spc)
+{
+ pcireg_t address;
+
+ KASSERT(spc != NULL);
+
+ address = pci_conf_read(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM);
+ address &= ~PCI_MAPREG_ROM_ENABLE;
+ pci_conf_write(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM, address);
+}
+
+void
+gftfb_disable_rom(struct sti_softc *sc)
+{
+ struct gftfb_softc *spc = device_private(sc->sc_dev);
+
+ if (ISSET(sc->sc_flags, STI_ROM_ENABLED)) {
+ gftfb_disable_rom_internal(spc);
+ }
+ CLR(sc->sc_flags, STI_ROM_ENABLED);
+}
+
+void
+gftfb_wait(struct gftfb_softc *sc)
+{
+ struct sti_rom *rom = sc->sc_base.sc_rom;
+ bus_space_tag_t memt = rom->memt;
+ bus_space_handle_t memh = rom->regh[2];
+ uint8_t stat;
+
+ do {
+ stat = bus_space_read_1(memt, memh, NGLE_REG_15b0);
+ if (stat == 0)
+ stat = bus_space_read_1(memt, memh, NGLE_REG_15b0);
+ } while (stat != 0);
+}
+
+void
+gftfb_setup_fb(struct gftfb_softc *sc)
+{
+ struct sti_rom *rom = sc->sc_base.sc_rom;
+ bus_space_tag_t memt = rom->memt;
+ bus_space_handle_t memh = rom->regh[2];
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_10, 0x13601000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_14, 0x83000300);
+ gftfb_wait(sc);
+ bus_space_write_1(memt, memh, NGLE_REG_16b1, 1);
+}
+
+void
+gftfb_setup(struct gftfb_softc *sc)
+{
+ struct sti_rom *rom = sc->sc_base.sc_rom;
+ bus_space_tag_t memt = rom->memt;
+ bus_space_handle_t memh = rom->regh[2];
+
+ /* set Bt458 read mask register to all planes */
+ gftfb_wait(sc);
+ ngle_bt458_write(memt, memh, 0x08, 0x04);
+ ngle_bt458_write(memt, memh, 0x0a, 0xff);
+
+ gftfb_setup_fb(sc);
+
+ /* attr. planes */
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_11, 0x2ea0d000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_14, 0x23000302);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_12, NGLE_ARTIST_CMAP0);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_8, 0xffffffff);
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_6, 0x00000000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_9,
+ (sc->sc_scr.scr_cfg.scr_width << 16) | sc->sc_scr.scr_cfg.scr_height);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_6, 0x05000000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_9, 0x00040001);
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_12, 0x00000000);
+
+ gftfb_setup_fb(sc);
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_21,
+ bus_space_read_stream_4(memt, memh, NGLE_REG_21) | 0x0a000000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_27,
+ bus_space_read_stream_4(memt, memh, NGLE_REG_27) | 0x00800000);
+}
+
+static int
+gftfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
+ struct lwp *l)
+{
+ struct vcons_data *vd = v;
+ struct gftfb_softc *sc = vd->cookie;
+ struct wsdisplay_fbinfo *wdf;
+ struct vcons_screen *ms = vd->active;
+
+ switch (cmd) {
+ case WSDISPLAYIO_GTYPE:
+ *(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
+ return 0;
+
+ /* PCI config read/write passthrough. */
+ case PCI_IOC_CFGREAD:
+ case PCI_IOC_CFGWRITE:
+ return pci_devioctl(sc->sc_pc, sc->sc_tag,
+ cmd, data, flag, l);
+
+ case WSDISPLAYIO_GET_BUSID:
+ return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
+ sc->sc_tag, data);
+
+ case WSDISPLAYIO_GINFO:
+ if (ms == NULL)
+ return ENODEV;
+ wdf = (void *)data;
+ wdf->height = ms->scr_ri.ri_height;
+ wdf->width = ms->scr_ri.ri_width;
+ wdf->depth = ms->scr_ri.ri_depth;
+ wdf->cmsize = 256;
+ return 0;
+
+ case WSDISPLAYIO_GETCMAP:
+ return gftfb_getcmap(sc,
+ (struct wsdisplay_cmap *)data);
+
+ case WSDISPLAYIO_PUTCMAP:
+ return gftfb_putcmap(sc,
+ (struct wsdisplay_cmap *)data);
+
+ case WSDISPLAYIO_LINEBYTES:
+ *(u_int *)data = 2048;
+ return 0;
+
+ case WSDISPLAYIO_SMODE: {
+ int new_mode = *(int*)data;
+ if (new_mode != sc->sc_mode) {
+ sc->sc_mode = new_mode;
+ if(new_mode == WSDISPLAYIO_MODE_EMUL) {
+ //r128fb_init(sc);
+ gftfb_restore_palette(sc);
+ //glyphcache_wipe(&sc->sc_gc);
+ //r128fb_rectfill(sc, 0, 0, sc->sc_width,
+ // sc->sc_height, ms->scr_ri.ri_devcmap[
+ // (ms->scr_defattr >> 16) & 0xff]);
+ vcons_redraw_screen(ms);
+ }
+ }
+ }
+ return 0;
+
+ case WSDISPLAYIO_GET_FBINFO:
+ {
+ struct wsdisplayio_fbinfo *fbi = data;
+
+ return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
+ }
+ }
+ return EPASSTHROUGH;
+}
+
+static paddr_t
+gftfb_mmap(void *v, void *vs, off_t offset, int prot)
+{
+#if 0
+ struct vcons_data *vd = v;
+ struct gftfb_softc *sc = vd->cookie;
+ paddr_t pa;
+#endif
+ return -1;
+}
+
+static void
+gftfb_init_screen(void *cookie, struct vcons_screen *scr,
+ int existing, long *defattr)
+{
+ struct gftfb_softc *sc = cookie;
+ struct rasops_info *ri = &scr->scr_ri;
+
+ ri->ri_depth = 8;
+ ri->ri_width = sc->sc_width;
+ ri->ri_height = sc->sc_height;
+ ri->ri_stride = 2048;
+ ri->ri_flg = RI_CENTER;
+ if (scr->scr_flags & VCONS_SCREEN_IS_STATIC)
+ ri->ri_flg |= RI_FULLCLEAR | RI_CLEAR;
+ ri->ri_bits = (void *)sc->sc_scr.fbaddr;
+#if 0
+ if (sc->sc_depth == 8)
+ ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA |
+ RI_PREFER_ALPHA;
+#endif
+ rasops_init(ri, 0, 0);
+ ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_UNDERLINE |
+ WSSCREEN_RESIZE;
+ scr->scr_flags |= VCONS_DONT_READ;
+ scr->scr_flags |= VCONS_LOADFONT;
+
+ rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight,
+ sc->sc_width / ri->ri_font->fontwidth);
+
+ ri->ri_hw = scr;
+#if 0
+ ri->ri_ops.copyrows = gftfb_copyrows;
+ ri->ri_ops.copycols = gftfb_copycols;
+ ri->ri_ops.eraserows = gftfb_eraserows;
+ ri->ri_ops.erasecols = gftfb_erasecols;
+ ri->ri_ops.cursor = gftfb_cursor;
+ if (FONT_IS_ALPHA(ri->ri_font)) {
+ ri->ri_ops.putchar = gftfb_putchar_aa;
+ } else
+ ri->ri_ops.putchar = gftfb_putchar;
+#endif
+}
+
+static int
+gftfb_putcmap(struct gftfb_softc *sc, struct wsdisplay_cmap *cm)
+{
+ u_char *r, *g, *b;
+ u_int index = cm->index;
+ u_int count = cm->count;
+ int i, error;
+ u_char rbuf[256], gbuf[256], bbuf[256];
+
+#ifdef R128FB_DEBUG
+ aprint_debug("putcmap: %d %d\n",index, count);
+#endif
+ if (cm->index >= 256 || cm->count > 256 ||
+ (cm->index + cm->count) > 256)
+ return EINVAL;
+ error = copyin(cm->red, &rbuf[index], count);
+ if (error)
+ return error;
+ error = copyin(cm->green, &gbuf[index], count);
+ if (error)
+ return error;
+ error = copyin(cm->blue, &bbuf[index], count);
+ if (error)
+ return error;
+
+ memcpy(&sc->sc_cmap_red[index], &rbuf[index], count);
+ memcpy(&sc->sc_cmap_green[index], &gbuf[index], count);
+ memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count);
+
+ r = &sc->sc_cmap_red[index];
+ g = &sc->sc_cmap_green[index];
+ b = &sc->sc_cmap_blue[index];
+
+ for (i = 0; i < count; i++) {
+ gftfb_putpalreg(sc, index, *r, *g, *b);
+ index++;
+ r++, g++, b++;
+ }
+ return 0;
+}
+
+static int
+gftfb_getcmap(struct gftfb_softc *sc, struct wsdisplay_cmap *cm)
+{
+ u_int index = cm->index;
+ u_int count = cm->count;
+ int error;
+
+ if (index >= 255 || count > 256 || index + count > 256)
+ return EINVAL;
+
+ error = copyout(&sc->sc_cmap_red[index], cm->red, count);
+ if (error)
+ return error;
+ error = copyout(&sc->sc_cmap_green[index], cm->green, count);
+ if (error)
+ return error;
+ error = copyout(&sc->sc_cmap_blue[index], cm->blue, count);
+ if (error)
+ return error;
+
+ return 0;
+}
+
+static void
+gftfb_restore_palette(struct gftfb_softc *sc)
+{
+ int i;
+
+ for (i = 0; i < 256; i++) {
+ gftfb_putpalreg(sc, i, sc->sc_cmap_red[i],
+ sc->sc_cmap_green[i], sc->sc_cmap_blue[i]);
+ }
+}
+
+static int
+gftfb_putpalreg(struct gftfb_softc *sc, uint8_t idx, uint8_t r, uint8_t g,
+ uint8_t b)
+{
+ struct sti_rom *rom = sc->sc_base.sc_rom;
+ bus_space_tag_t memt = rom->memt;
+ bus_space_handle_t memh = rom->regh[2];
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_10, 0xbbe0f000);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_14, 0x03000300);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_13, 0xffffffff);
+
+ gftfb_wait(sc);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_3,
+ 0x400 | (idx << 2));
+ bus_space_write_stream_4(memt, memh, NGLE_REG_4,
+ (r << 16) | (g << 8) | b);
+
+ bus_space_write_stream_4(memt, memh, NGLE_REG_2, 0x400);
+ bus_space_write_stream_4(memt, memh, NGLE_REG_26, 0x80000100);
+ gftfb_setup_fb(sc);
+ return 0;
+}
