Module Name: src
Committed By: skrll
Date: Fri Feb 16 15:11:17 UTC 2024
Modified Files:
src/sys/arch/arm/broadcom: bcm53xx_board.c bcm53xx_cca.c bcm53xx_idm.c
bcm53xx_pax.c bcm53xx_reg.h
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/arm/broadcom/bcm53xx_board.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/broadcom/bcm53xx_cca.c
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/broadcom/bcm53xx_idm.c
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/broadcom/bcm53xx_pax.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/broadcom/bcm53xx_reg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/broadcom/bcm53xx_board.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_board.c:1.25 src/sys/arch/arm/broadcom/bcm53xx_board.c:1.26
--- src/sys/arch/arm/broadcom/bcm53xx_board.c:1.25 Tue Jul 31 06:46:25 2018
+++ src/sys/arch/arm/broadcom/bcm53xx_board.c Fri Feb 16 15:11:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_board.c,v 1.25 2018/07/31 06:46:25 skrll Exp $ */
+/* $NetBSD: bcm53xx_board.c,v 1.26 2024/02/16 15:11:17 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.25 2018/07/31 06:46:25 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.26 2024/02/16 15:11:17 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -328,7 +328,7 @@ bcm53xx_usb_clock_init(struct bcm53xx_cl
const uint32_t ndiv = bcm53xx_value_wrap(usb2_control,
USB2_CONTROL_NDIV_INT);
- uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv;
+ uint32_t usb_ref = (clk->clk_usb2 / pdiv) * ndiv;
if (usb_ref != USB2_REF_CLK) {
/*
* USB Reference Clock isn't 1.92GHz. So we need to modify
@@ -350,7 +350,7 @@ bcm53xx_usb_clock_init(struct bcm53xx_cl
bus_space_write_4(bcm53xx_ioreg_bst, bcm53xx_ioreg_bsh,
CRU_BASE + CRU_CLKSET_KEY, 0);
- usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv;
+ usb_ref = (clk->clk_usb2 / pdiv) * new_ndiv;
}
clk->clk_usb_ref = usb_ref;
@@ -367,7 +367,7 @@ bcm53xx_clock_init(struct bcm53xx_clock_
/*
* F(ddr) = ((1 / pdiv) * ndiv * CH2) / (post_div * 2)
*/
-static void
+static void
bcm53xx_get_ddr_freq(struct bcm53xx_clock_info *clk, uint32_t pll_status,
uint32_t pll_dividers)
{
@@ -402,7 +402,7 @@ bcm53xx_get_cpu_freq(struct bcm53xx_cloc
clk->clk_apb = clk->clk_cpu / 4;
return;
}
-
+
const u_int pdiv = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_PDIV);
const u_int ndiv_int = bcm53xx_value_wrap(pllarma, CLK_PLLARMA_NDIV_INT);
const u_int ndiv_frac = __SHIFTOUT(pllarmb, CLK_PLLARMB_NDIV_FRAC);
@@ -605,13 +605,13 @@ bcm53xx_device_register(device_t self, v
* XXX KLUDGE ALERT XXX
* The iot mainbus supplies is completely wrong since it scales
* addresses by 2. The simplest remedy is to replace with our
- * bus space used for the armcore registers (which armperiph uses).
+ * bus space used for the armcore registers (which armperiph uses).
*/
struct mainbus_attach_args * const mb = aux;
mb->mb_iot = bcm53xx_armcore_bst;
return;
}
-
+
/*
* We need to tell the A9 Global/Watchdog Timer
* what frequency it runs at.
@@ -649,8 +649,8 @@ bcm53xx_srab_init(void)
{
mutex_init(&srab_lock, MUTEX_DEFAULT, IPL_VM);
- bcm53xx_srab_write_4(0x0079, 0x90); // reset switch
- for (u_int port = 0; port < 8; port++) {
+ bcm53xx_srab_write_4(0x0079, 0x90); // reset switch
+ for (u_int port = 0; port < 8; port++) {
/* per port control: no stp */
bcm53xx_srab_write_4(port, 0x00);
}
Index: src/sys/arch/arm/broadcom/bcm53xx_cca.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_cca.c:1.5 src/sys/arch/arm/broadcom/bcm53xx_cca.c:1.6
--- src/sys/arch/arm/broadcom/bcm53xx_cca.c:1.5 Thu Mar 3 06:26:28 2022
+++ src/sys/arch/arm/broadcom/bcm53xx_cca.c Fri Feb 16 15:11:17 2024
@@ -43,7 +43,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_cca.c,v 1.5 2022/03/03 06:26:28 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_cca.c,v 1.6 2024/02/16 15:11:17 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -143,7 +143,7 @@ bcmcca_intr(void *arg)
}
}
if (v & INTSTATUS_GPIOINT) {
-
+
}
return rv;
}
Index: src/sys/arch/arm/broadcom/bcm53xx_idm.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_idm.c:1.3 src/sys/arch/arm/broadcom/bcm53xx_idm.c:1.4
--- src/sys/arch/arm/broadcom/bcm53xx_idm.c:1.3 Wed Dec 12 00:01:28 2012
+++ src/sys/arch/arm/broadcom/bcm53xx_idm.c Fri Feb 16 15:11:17 2024
@@ -35,7 +35,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_idm.c,v 1.3 2012/12/12 00:01:28 matt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_idm.c,v 1.4 2024/02/16 15:11:17 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -59,7 +59,7 @@ struct idm_info {
static bool
bcmeth_unreset(bus_space_tag_t bst, bus_space_handle_t bsh,
const struct idm_info *idm)
-{
+{
/*
* To enable any GMAC, we must enable all off them.
*/
Index: src/sys/arch/arm/broadcom/bcm53xx_pax.c
diff -u src/sys/arch/arm/broadcom/bcm53xx_pax.c:1.23 src/sys/arch/arm/broadcom/bcm53xx_pax.c:1.24
--- src/sys/arch/arm/broadcom/bcm53xx_pax.c:1.23 Fri Feb 16 12:08:29 2024
+++ src/sys/arch/arm/broadcom/bcm53xx_pax.c Fri Feb 16 15:11:17 2024
@@ -34,7 +34,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.23 2024/02/16 12:08:29 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_pax.c,v 1.24 2024/02/16 15:11:17 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -269,7 +269,7 @@ bcmpax_ccb_attach(device_t parent, devic
aprint_error_dev(self,
"failed to establish interrupt #%zu (%zu)\n", i,
loc->loc_intrs[0] + i);
- while (i-- > 0) {
+ while (i-- > 0) {
intr_disestablish(sc->sc_ih[i]);
}
return;
@@ -292,7 +292,7 @@ bcmpax_ccb_attach(device_t parent, devic
* This will force the device to negotiate to a max of gen1.
*/
if (cf->cf_flags & 1) {
- bcmpax_conf_write(sc, 0, offset + PCIE_LCSR2, 1);
+ bcmpax_conf_write(sc, 0, offset + PCIE_LCSR2, 1);
}
/*
@@ -300,7 +300,7 @@ bcmpax_ccb_attach(device_t parent, devic
*/
offset += PCIE_LCSR;
for (size_t timo = 0;; timo++) {
- const pcireg_t lcsr = bcmpax_conf_read(sc, 0, offset);
+ const pcireg_t lcsr = bcmpax_conf_read(sc, 0, offset);
sc->sc_linkup = __SHIFTOUT(lcsr, PCIE_LCSR_NLW) != 0
&& (1 || (lcsr & PCIE_LCSR_DLACTIVE) != 0);
if (sc->sc_linkup || timo == 250) {
@@ -358,7 +358,7 @@ bcmpax_ccb_attach(device_t parent, devic
struct pcibus_attach_args pba;
memset(&pba, 0, sizeof(pba));
-
+
pba.pba_flags = sc->sc_pba_flags;
pba.pba_flags |= PCI_FLAGS_MEM_OKAY;
pba.pba_memt = sc->sc_bst;
@@ -395,7 +395,7 @@ bcmpax_decompose_tag(void *v, pcitag_t t
*devp = __SHIFTOUT(tag, CFG_ADDR_DEV);
if (funcp)
*funcp = __SHIFTOUT(tag, CFG_ADDR_FUNC);
-}
+}
static pcitag_t
bcmpax_make_tag(void *v, int bus, int dev, int func)
@@ -422,7 +422,7 @@ bcmpax_conf_addr_write(struct bcmpax_sof
bcmpax_write_4(sc, PCIE_CFG_ADDR, tag);
dsb(sy);
return PCIE_CFG_DATA;
- }
+ }
return 0;
}
Index: src/sys/arch/arm/broadcom/bcm53xx_reg.h
diff -u src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.19 src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.20
--- src/sys/arch/arm/broadcom/bcm53xx_reg.h:1.19 Thu Mar 24 08:08:04 2022
+++ src/sys/arch/arm/broadcom/bcm53xx_reg.h Fri Feb 16 15:11:17 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm53xx_reg.h,v 1.19 2022/03/24 08:08:04 andvar Exp $ */
+/* $NetBSD: bcm53xx_reg.h,v 1.20 2024/02/16 15:11:17 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -338,7 +338,7 @@
#define CRU_GENPLL_CONTROL6 0x1158
#define GENPLL_CONTROL6_PDIV __BITS(26,24) // = (n ? n : 8)
#define GENPLL_CONTROL6_CH0_MDIV __BITS(23,16) // = (n ? n : 256), clk_mac
-#define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo
+#define GENPLL_CONTROL6_CH1_MDIV __BITS(15,8) // = (n ? n : 256), clk_robo
#define GENPLL_CONTROL6_CH2_MDIV __BITS(7,0) // = (n ? n : 256), clf_usb2
#define CRU_GENPLL_CONTROL7 0x115c
#define GENPLL_CONTROL7_CH3_MDIV __BITS(23,16) // = (n ? n : 256), clk_iproc
@@ -348,7 +348,7 @@
#define USB2_CONTROL_KA __BITS(24,22)
#define USB2_CONTROL_KI __BITS(31,19)
#define USB2_CONTROL_KP __BITS(18,15)
-#define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8)
+#define USB2_CONTROL_PDIV __BITS(14,12) // = (n ? n : 8)
#define USB2_CONTROL_NDIV_INT __BITS(11,2) // = (n ? n : 1024)
#define USB2_CONTROL_PLL_PCIEUSB3_RESET __BIT(1) // inverted 1=normal
#define USB2_CONTROL_PLL_USB2_RESET __BIT(0) // inverted 1=normal
@@ -386,7 +386,7 @@
#define DMU_LCPLL_CONTROL0 0x100
#define DMU_LCPLL_CONTROL1 0x104
-#define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8)
+#define LCPLL_CONTROL1_PDIV __BITS(30,28) // = (n ? n : 8)
#define LCPLL_CONTROL1_NDIV_INT __BITS(27,20) // = (n ? n : 256)
#define LCPLL_CONTROL1_NDIV_FRAC __BITS(19,0) // = 1 / n
/*
@@ -395,7 +395,7 @@
#define DMU_LCPLL_CONTROL2 0x108
#define LCPLL_CONTROL2_CH0_MDIV __BITS(31,24) // = (n ? n : 256), clk_pcie_ref
#define LCPLL_CONTROL2_CH1_MDIV __BITS(23,16) // = (n ? n : 256), clk_sdio
-#define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr
+#define LCPLL_CONTROL2_CH2_MDIV __BITS(15,8) // = (n ? n : 256), clk_ddr
#define LCPLL_CONTROL2_CH3_MDIV __BITS(7,0) // = (n ? n : 256), clf_dft
#define DMU_CRU_RESET 0x200
@@ -651,7 +651,7 @@
#define CLK_APB_DIV_TRIGGER_OVERRIDE __BIT(0)
#define ARMCORE_CLK_PLLARMA 0xc00
-#define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?))
+#define CLK_PLLARMA_PDIV __BITS(26,24) // = (n ? n : 16(?))
#define CLK_PLLARMA_NDIV_INT __BITS(17,8) // = (n ? n : 1024)
#define ARMCORE_CLK_PLLARMB 0xc04
@@ -777,7 +777,7 @@ struct gmac_rxdb {
#define GMAC_BISTSTATUS 0x00c
#define GMAC_INTSTATUS 0x020
#define GMAC_INTMASK 0x024
-#define TXQECCUNCORRECTED __BIT(31)
+#define TXQECCUNCORRECTED __BIT(31)
#define TXQECCCORRECTED __BIT(30)
#define RXQECCUNCORRECTED __BIT(29)
#define RXQECCCORRECTED __BIT(28)
@@ -904,18 +904,18 @@ struct gmac_rxdb {
#define RX_LOW_LATENCY_EN __BIT(11)
#define HD_ENA __BIT(10)
#define TX_ADDR_INS __BIT(9)
-#define PAUSE_IGNORE __BIT(8)
-#define PAUSE_FWD __BIT(7)
-#define CRC_FWD __BIT(6)
-#define PAD_EN __BIT(5)
-#define PROMISC_EN __BIT(4)
+#define PAUSE_IGNORE __BIT(8)
+#define PAUSE_FWD __BIT(7)
+#define CRC_FWD __BIT(6)
+#define PAD_EN __BIT(5)
+#define PROMISC_EN __BIT(4)
#define ETH_SPEED __BITS(3,2)
#define ETH_SPEED_10 0
#define ETH_SPEED_100 1
#define ETH_SPEED_1000 2
#define ETH_SPEED_2500 3
-#define RX_ENA __BIT(1)
-#define TX_ENA __BIT(0)
+#define RX_ENA __BIT(1)
+#define TX_ENA __BIT(0)
#define UNIMAC_MAC_0 0x80c // bits 16:47 of macaddr
#define UNIMAC_MAC_1 0x810 // bits 0:15 of macaddr
#define UNIMAC_FRAME_LEN 0x814
