Module Name: src
Committed By: skrll
Date: Sat Apr 6 10:08:54 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: files.riscv
src/sys/arch/riscv/include: types.h
src/sys/arch/riscv/riscv: genassym.cf
Added Files:
src/sys/arch/riscv/riscv: copy.S
Log Message:
Provide and use _ucas_{32,64} implementations
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/riscv/include/types.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/riscv/copy.S
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/genassym.cf
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.14 src/sys/arch/riscv/conf/files.riscv:1.15
--- src/sys/arch/riscv/conf/files.riscv:1.14 Sun Sep 3 08:48:19 2023
+++ src/sys/arch/riscv/conf/files.riscv Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.14 2023/09/03 08:48:19 skrll Exp $
+# $NetBSD: files.riscv,v 1.15 2024/04/06 10:08:54 skrll Exp $
#
maxpartitions 16
@@ -25,6 +25,7 @@ file arch/riscv/riscv/bus_space_generic.
file arch/riscv/riscv/bus_space_notimpl.S
file arch/riscv/riscv/bus_stubs.c
file arch/riscv/riscv/clock_machdep.c
+file arch/riscv/riscv/copy.S
file arch/riscv/riscv/core_machdep.c coredump
file arch/riscv/riscv/cpu.c cpu
file arch/riscv/riscv/cpu_subr.c
Index: src/sys/arch/riscv/include/types.h
diff -u src/sys/arch/riscv/include/types.h:1.16 src/sys/arch/riscv/include/types.h:1.17
--- src/sys/arch/riscv/include/types.h:1.16 Sun May 7 12:41:48 2023
+++ src/sys/arch/riscv/include/types.h Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: types.h,v 1.16 2023/05/07 12:41:48 skrll Exp $ */
+/* $NetBSD: types.h,v 1.17 2024/04/06 10:08:54 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -98,6 +98,7 @@ typedef __int32_t __register_t;
#define __HAVE_NEW_STYLE_BUS_H
#define __HAVE_SYSCALL_INTERN
#define __HAVE_TLS_VARIANT_I
+#define __HAVE_UCAS_FULL
/* XXX temporary */
#define __HAVE_UNLOCKED_PMAP
#define __HAVE___LWP_GETPRIVATE_FAST
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.15 src/sys/arch/riscv/riscv/genassym.cf:1.16
--- src/sys/arch/riscv/riscv/genassym.cf:1.15 Mon Jun 12 19:04:14 2023
+++ src/sys/arch/riscv/riscv/genassym.cf Sat Apr 6 10:08:54 2024
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.15 2023/06/12 19:04:14 skrll Exp $
+# $NetBSD: genassym.cf,v 1.16 2024/04/06 10:08:54 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -148,6 +148,7 @@ define CI_MTX_COUNT offsetof(struct cpu_
define CI_MTX_OLDSPL offsetof(struct cpu_info, ci_mtx_oldspl)
define CI_SOFTINTS offsetof(struct cpu_info, ci_softints)
+define FB_LEN sizeof(struct faultbuf)
define FB_A0 offsetof(struct faultbuf, fb_reg[FB_A0])
define FB_RA offsetof(struct faultbuf, fb_reg[FB_RA])
define FB_S0 offsetof(struct faultbuf, fb_reg[FB_S0])
@@ -165,6 +166,8 @@ define FB_S11 offsetof(struct faultbuf,
define FB_SP offsetof(struct faultbuf, fb_reg[FB_SP])
define FB_SR offsetof(struct faultbuf, fb_sr)
+define EFAULT EFAULT
+
define PAGE_SIZE PAGE_SIZE
define PAGE_MASK PAGE_MASK
define PAGE_SHIFT PAGE_SHIFT
@@ -192,6 +195,7 @@ define RW_WRITE_LOCKED RW_WRITE_LOCKED
define RW_READ_INCR RW_READ_INCR
define RW_READER RW_READER
+define VM_MAXUSER_ADDRESS VM_MAXUSER_ADDRESS
define VM_MIN_KERNEL_ADDRESS VM_MIN_KERNEL_ADDRESS
define VM_MAX_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS
define VM_KERNEL_BASE VM_KERNEL_BASE
Added files:
Index: src/sys/arch/riscv/riscv/copy.S
diff -u /dev/null src/sys/arch/riscv/riscv/copy.S:1.1
--- /dev/null Sat Apr 6 10:08:54 2024
+++ src/sys/arch/riscv/riscv/copy.S Sat Apr 6 10:08:54 2024
@@ -0,0 +1,158 @@
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+#include "assym.h"
+
+#define UCAS_FRAME_SIZE (FB_LEN + 4 * SZREG)
+#define UCAS_FRAME_A0 (UCAS_FRAME_SIZE - 4 * SZREG)
+#define UCAS_FRAME_A1 (UCAS_FRAME_SIZE - 3 * SZREG)
+#define UCAS_FRAME_S0 (UCAS_FRAME_SIZE - 2 * SZREG)
+#define UCAS_FRAME_RA (UCAS_FRAME_SIZE - 1 * SZREG)
+
+.macro enter_ucas
+ addi sp, sp, -UCAS_FRAME_SIZE
+ REG_S a0, UCAS_FRAME_A0(sp)
+ REG_S a1, UCAS_FRAME_A1(sp)
+ REG_S s0, UCAS_FRAME_S0(sp)
+ REG_S ra, UCAS_FRAME_RA(sp)
+ addi s0, sp, UCAS_FRAME_SIZE
+.endm
+
+.macro exit_ucas
+ REG_L s0, UCAS_FRAME_S0(sp)
+ REG_L ra, UCAS_FRAME_RA(sp)
+ addi sp, sp, UCAS_FRAME_SIZE
+.endm
+
+.macro enter_cpu_onfault
+ // error = cpu_set_onfault(&fb, EFAULT);
+ mv a0, sp
+ li a1, EFAULT
+ call cpu_set_onfault
+ // if (error) goto fail;
+ bnez a0, 9f
+.endm
+
+.macro exit_cpu_onfault
+ // curlwp->l_md.md_onfault = NULL;
+ REG_S zero, L_MD_ONFAULT(tp)
+.endm
+
+.macro set_sum
+ // csr_sstatus_set(SR_SUM);
+ li t1, SR_SUM
+ csrs sstatus, t1
+.endm
+
+.macro clear_sum
+ // csr_sstatus_clear(SR_SUM);
+ li t1, SR_SUM
+ csrc sstatus, t1
+.endm
+
+
+/*
+ * int _ucas_32(volatile uint32_t *ptr, uint32_t old,
+ * uint32_t new, uint32_t *ret)
+ *
+ * Implies release/acquire barriers until someone tells me
+ * otherwise about _ucas_32/64.
+ */
+ENTRY(_ucas_32)
+ li t0, (VM_MAXUSER_ADDRESS - 4)
+ bltu t0, a0, 3f
+
+ enter_ucas
+
+ enter_cpu_onfault
+
+ REG_L t0, UCAS_FRAME_A0(sp)
+ REG_L a1, UCAS_FRAME_A1(sp)
+
+ set_sum
+
+1: lr.w a0, 0(t0) /* load old value */
+ bne a0, a1, 2f /* return if different */
+ sc.w t1, a2, 0(t0) /* store new value */
+ bnez t1, 1b /* succeed? nope, try again. */
+2:
+ clear_sum
+
+ sw a0, 0(a3)
+
+ exit_cpu_onfault
+ li a0, 0 // success
+9:
+ exit_ucas
+ ret
+3:
+ li a0, EFAULT
+ ret
+END(_ucas_32)
+
+
+/*
+ * int _ucas_64(volatile uint64_t *ptr, uint64_t old,
+ * uint64_t new, uint64_t *ret)
+ *
+ * Implies release/acquire barriers until someone tells me
+ * otherwise about _ucas_32/64.
+ */
+ENTRY(_ucas_64)
+ li t0, (VM_MAXUSER_ADDRESS - 8)
+ bltu t0, a0, 3f
+
+ enter_ucas
+
+ enter_cpu_onfault
+
+ REG_L t0, (FB_LEN + 0 * SZREG)(sp)
+ REG_L a1, (FB_LEN + 1 * SZREG)(sp)
+
+ set_sum
+
+1: lr.d a0, 0(t0) /* load old value */
+ bne a1, a0, 2f /* return if different */
+ sc.d t1, a2, 0(t0) /* store new value */
+ bnez t1, 1b /* succeed? nope, try again. */
+2:
+ clear_sum
+
+ sd a0, 0(a3)
+
+ exit_cpu_onfault
+ li a0, 0 // success
+9:
+ exit_ucas
+ ret
+3:
+ li a0, EFAULT
+ ret
+END(_ucas_64)
