Module Name: src
Committed By: rillig
Date: Sun Apr 7 17:08:00 UTC 2024
Modified Files:
src/sys/arch/sparc/include: psl.h
src/sys/arch/sparc/sparc: memeccreg.h
src/sys/arch/sparc64/include: psl.h
Log Message:
sparc: fix typos and omissions in PSTATE_BITS and ECC_AFR_BITS
Fixes PR 57869.
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/sparc/include/psl.h
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/sparc/sparc/memeccreg.h
cvs rdiff -u -r1.64 -r1.65 src/sys/arch/sparc64/include/psl.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sparc/include/psl.h
diff -u src/sys/arch/sparc/include/psl.h:1.52 src/sys/arch/sparc/include/psl.h:1.53
--- src/sys/arch/sparc/include/psl.h:1.52 Tue Jul 11 13:10:08 2023
+++ src/sys/arch/sparc/include/psl.h Sun Apr 7 17:08:00 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: psl.h,v 1.52 2023/07/11 13:10:08 martin Exp $ */
+/* $NetBSD: psl.h,v 1.53 2024/04/07 17:08:00 rillig Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -113,8 +113,11 @@
#define PSTATE_IE 0x002 /* interrupt enable */
#define PSTATE_AG 0x001 /* enable alternate globals */
-#define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
-
+#define PSTATE_BITS "\177\020" \
+ "b\013IG\0" "b\012MG\0" "b\011CLE\0" "b\010TLE\0" \
+ "F\006\002\0" ":\000MM_TSO\0" ":\001MM_PSO\0" \
+ ":\002MM_RMO\0" "*?\0" "b\005RED\0" "b\004PEF\0" \
+ "b\003AM\0" "b\002PRIV\0" "b\001IE\0" "b\000AG\0"
/*
* 32-bit code requires TSO or at best PSO since that's what's supported on
Index: src/sys/arch/sparc/sparc/memeccreg.h
diff -u src/sys/arch/sparc/sparc/memeccreg.h:1.2 src/sys/arch/sparc/sparc/memeccreg.h:1.3
--- src/sys/arch/sparc/sparc/memeccreg.h:1.2 Mon Apr 28 20:23:36 2008
+++ src/sys/arch/sparc/sparc/memeccreg.h Sun Apr 7 17:08:00 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: memeccreg.h,v 1.2 2008/04/28 20:23:36 martin Exp $ */
+/* $NetBSD: memeccreg.h,v 1.3 2024/04/07 17:08:00 rillig Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -73,7 +73,7 @@
#define ECC_AFR_S 0x08000000 /* Access was in supervisor mode */
#define ECC_AFR_MID 0xf0000000 /* Module code */
#define ECC_AFR_BITS "\177\020" \
- "f\0\4VAH\0f\4\4TYPE\0f\10\3SIZE\0" \
+ "f\0\4PAH\0f\4\4TYPE\0f\10\3SIZE\0" \
"b\13C\0b\14LOCK\0b\15MBL\0" \
"f\16\10VA\0b\33S\0f\34\4MID\0"
Index: src/sys/arch/sparc64/include/psl.h
diff -u src/sys/arch/sparc64/include/psl.h:1.64 src/sys/arch/sparc64/include/psl.h:1.65
--- src/sys/arch/sparc64/include/psl.h:1.64 Sat Sep 2 05:51:57 2023
+++ src/sys/arch/sparc64/include/psl.h Sun Apr 7 17:08:00 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: psl.h,v 1.64 2023/09/02 05:51:57 jdc Exp $ */
+/* $NetBSD: psl.h,v 1.65 2024/04/07 17:08:00 rillig Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -129,7 +129,11 @@
#define PSTATE_IE 0x002 /* interrupt enable */
#define PSTATE_AG 0x001 /* enable alternate globals */
-#define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
+#define PSTATE_BITS "\177\020" \
+ "b\013IG\0" "b\012MG\0" "b\011CLE\0" "b\010TLE\0" \
+ "F\006\002\0" ":\000MM_TSO\0" ":\001MM_PSO\0" \
+ ":\002MM_RMO\0" "*?\0" "b\005RED\0" "b\004PEF\0" \
+ "b\003AM\0" "b\002PRIV\0" "b\001IE\0" "b\000AG\0"
/*
