Module Name: src
Committed By: msaitoh
Date: Thu Oct 17 14:22:35 UTC 2024
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
x86/specialreg.h: Update AMD CPUID definitions.
Update definitions from the following PPR:
- PPR for AMD Family 19h Model 11h, Revision B2 Processors
(Doc ID 55901 rev. 0.47)
- PPR for AMD Family 1Ah Model 02h, Revision C1 Processors
(Doc ID 57238 rev.0.24)
- PPR for AMD Family 1Ah Model 24h, Revision B0 Processors
(Doc ID 57274 rev. 3.00)
- Rename CPUID Fn8000001b EDX bit 11 from IbsL3MissFiltering to
Zen4IbsExtension.
- Add some CPUID bits.
To generate a diff of this commit:
cvs rdiff -u -r1.214 -r1.215 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.214 src/sys/arch/x86/include/specialreg.h:1.215
--- src/sys/arch/x86/include/specialreg.h:1.214 Sun Oct 6 09:32:31 2024
+++ src/sys/arch/x86/include/specialreg.h Thu Oct 17 14:22:35 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.214 2024/10/06 09:32:31 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.215 2024/10/17 14:22:35 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -945,6 +945,7 @@
#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
#define CPUID_AMD_SVM_IDLEHLTINTERCEPT __BIT(30) /* Idle HLT Intercept */
+#define CPUID_AMD_SVM_ESHUTDOWN __BIT(31) /* Enhanced Shutdown Intr. */
#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
@@ -957,7 +958,7 @@
"\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
"\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
"\35VmcbAddrChkChg" "\36BusLockThreshold" "\37IdleHltIntercept" \
- "\40B31"
+ "\40EnhancedShutdownInterrupt"
/*
* AMD Instruction-Based Sampling Capabilities.
@@ -975,15 +976,17 @@
#define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */
#define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */
#define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */
-#define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */
+#define CPUID_IBS_ZEN4E __BIT(11) /* Zen4 IBS Extensions */
+#define CPUID_IBS_LOADLATFILT __BIT(12) /* Load Latency Filtering */
+#define CPUID_IBS_UPDDTLBSTAT __BIT(19) /* Updated DTLB stats */
#define CPUID_IBS_FLAGS "\20" \
"\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \
"\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \
"\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \
- "\14IbsL3MissFiltering" \
- "\15B12" \
- "\24B19"
+ "\14Zen4IbsExtensions" \
+ "\15IbsLoadLatencyFiltering" \
+ "\24IbsUpdtdDtlbStats"
/*
* AMD Cache Topology Information.
@@ -1078,20 +1081,41 @@
#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */
#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */
#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
+#define CPUID_AMDEXT2_PMCPRECISERETIRE __BIT(12) /* PMC Presize Retire */
#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
+
+#define CPUID_AMDEXT2_L2TLBSIZEX32 __BIT(14) /* L2TLB size encoded as x32 */
+#define CPUID_AMDEXT2_ERMSB __BIT(15) /* AMD implementation of ERMSB */
+#define CPUID_AMDEXT2_ __BIT(16) /* */
+
+
#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
+#define CPUID_AMDEXT2_0F017_RECLAIM __BIT(19) /* Opecode 0f 01/7 reserved */
+#define CPUID_AMDEXT2_PREFETCHI __BIT(20) /* IC prefetch support */
+#define CPUID_AMDEXT2_FP512_DOWNGRADE __BIT(21) /* FP512 dpath down to 256 */
+#define CPUID_AMDEXT2_WL_CLASS __BIT(22) /* wkld based heuristic feedback */
+#define CPUID_AMDEXT2_ERAPS __BIT(24) /* Enhn. Retn. Addr. Pred. Sec. */
+#define CPUID_AMDEXT2_SBPB __BIT(27) /* Selective Brnc. Pred. Barrier */
+#define CPUID_AMDEXT2_IBPB_BRTYPE __BIT(28) /* BRanch TYPE prediction flush */
+#define CPUID_AMDEXT2_SRSO_NO __BIT(29) /* Not vulnerable to SRSO */
+#define CPUID_AMDEXT2_SRSO_UK_NO __BIT(30) /* SRSO_NO at user-kern boundary */
+#define CPUID_AMDEXT2_SRSO_MSR_FIX __BIT(31) /* SRSO mitig. bit in BP_CFG[4] */
+
#define CPUID_AMDEXT2_FLAGS "\20" \
"\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
"\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \
"\7NullSelectClearsBase" "\10UpperAddressIgnore" \
"\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \
- "\15B12" "\16PrefetchCtlMSR" "\17B14" "\20B15" \
- "\21B16" "\22CpuidUserDis" "\23EPSF" "\24B19" \
- "\25B20" "\26B21" \
- "\31B24" "\34B27" \
- "\35B28" "\37B30"
+ "\15PMC2PreciseRetire" "\16PrefetchCtlMSR" "\17L2TlbsizeX32" \
+ "\20AMD_ERMSB" \
+ "\21OPCODE_0F017_RECLAIM" "\22CpuidUserDis" "\23EPSF" \
+ "\24FAST_REP_SCASB" \
+ "\25PREFETCHI" "\26FP512_DOWNGRADE" "\27WL_CLASS_SUPPORT" \
+ "\31ERAPS" "\34SBPB" \
+ "\35IBPB_BRTYPE" "\36SRSO_NO" "\37SRSO_USER_KERNEL_NO" \
+ "\40SRSO_MSR_FIX"
/*
* AMD Extended Performance Monitoring and Debug
