Module Name: src
Committed By: msaitoh
Date: Sat Oct 19 16:32:43 UTC 2024
Modified Files:
src/usr.sbin/cpuctl/arch: i386.c
Log Message:
cpuctl(x86): Calculate L2 TLB size using with CPUID_AMDEXT2_L2TLBSIZEX32.
It's required to calculate L2 TLB size correctly on Zen5.
To generate a diff of this commit:
cvs rdiff -u -r1.145 -r1.146 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.145 src/usr.sbin/cpuctl/arch/i386.c:1.146
--- src/usr.sbin/cpuctl/arch/i386.c:1.145 Sat Oct 19 06:36:38 2024
+++ src/usr.sbin/cpuctl/arch/i386.c Sat Oct 19 16:32:43 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.145 2024/10/19 06:36:38 msaitoh Exp $ */
+/* $NetBSD: i386.c,v 1.146 2024/10/19 16:32:43 msaitoh Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.145 2024/10/19 06:36:38 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.146 2024/10/19 16:32:43 msaitoh Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -1186,6 +1186,7 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
struct x86_cache_info *cai;
u_int descs[4];
u_int lfunc;
+ bool l2tlbx32 = false;
/* K5 model 0 has none of this info. */
if (ci->ci_family == 5 && ci->ci_model == 0)
@@ -1238,10 +1239,15 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
return;
/* Determine L2 cache/TLB info. */
+ if (lfunc >= 0x80000021) {
+ x86_cpuid(0x80000021, descs);
+ l2tlbx32 = descs[0] & CPUID_AMDEXT2_L2TLBSIZEX32;
+ }
x86_cpuid(0x80000006, descs);
cai = &ci->ci_cinfo[CAI_L2_ITLB];
- cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
+ cai->cai_totalsize =
+ AMD_L2_EBX_IUTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1);
cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
@@ -1252,7 +1258,8 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = 0; /* XXX Unknown/reserved */
cai = &ci->ci_cinfo[CAI_L2_ITLB2];
- cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
+ cai->cai_totalsize =
+ AMD_L2_EAX_IUTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1);
cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
@@ -1263,7 +1270,8 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = 0; /* XXX Unknown/reserved */
cai = &ci->ci_cinfo[CAI_L2_DTLB];
- cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
+ cai->cai_totalsize =
+ AMD_L2_EBX_DTLB_ENTRIES(descs[1]) * (l2tlbx32 ? 32 : 1);
cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
cai->cai_linesize = (4 * 1024);
cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
@@ -1274,7 +1282,8 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
cai->cai_associativity = 0; /* XXX Unknown/reserved */
cai = &ci->ci_cinfo[CAI_L2_DTLB2];
- cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
+ cai->cai_totalsize =
+ AMD_L2_EAX_DTLB_ENTRIES(descs[0]) * (l2tlbx32 ? 32 : 1);
cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
cai->cai_linesize = largepagesize;
cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
