Module Name: src
Committed By: skrll
Date: Sat Oct 26 15:49:43 UTC 2024
Modified Files:
src/sys/arch/riscv/conf: GENERIC64
src/sys/arch/riscv/starfive: files.starfive
Added Files:
src/sys/arch/riscv/starfive: jh7100_gmac.c jh7110_eqos.c jh71x0_eth.c
jh71x0_eth.h
Log Message:
risc-v: add ethernet support on JH71[01]0 support
At present only the JH7110 EQOS support is enabled as it work.
The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/riscv/conf/GENERIC64
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/starfive/files.starfive
cvs rdiff -u -r0 -r1.1 src/sys/arch/riscv/starfive/jh7100_gmac.c \
src/sys/arch/riscv/starfive/jh7110_eqos.c \
src/sys/arch/riscv/starfive/jh71x0_eth.c \
src/sys/arch/riscv/starfive/jh71x0_eth.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/GENERIC64
diff -u src/sys/arch/riscv/conf/GENERIC64:1.11 src/sys/arch/riscv/conf/GENERIC64:1.12
--- src/sys/arch/riscv/conf/GENERIC64:1.11 Mon Aug 19 07:33:55 2024
+++ src/sys/arch/riscv/conf/GENERIC64 Sat Oct 26 15:49:43 2024
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC64,v 1.11 2024/08/19 07:33:55 skrll Exp $
+# $NetBSD: GENERIC64,v 1.12 2024/10/26 15:49:43 skrll Exp $
#
# GENERIC machine description file
#
@@ -90,5 +90,14 @@ usb* at usbus?
include "dev/usb/usbdevices.config"
midi* at midibus?
+# Ethernet
+#awge* at fdt? # DesignWare Gigabit Ethernet
+eqos* at fdt? # DesignWare Ethernet QoS
+
+# MII/PHY support
+micphy* at mii? phy ? # Micrel KSZ[89]xxx PHYs
+mcommphy* at mii? phy ? # Motorcomm YT8511C/YT8511H PHYs
+ukphy* at mii? phy ? # generic unknown PHYs
+
# Pull in optional local configuration - always at end
cinclude "arch/riscv/conf/GENERIC64.local"
Index: src/sys/arch/riscv/starfive/files.starfive
diff -u src/sys/arch/riscv/starfive/files.starfive:1.4 src/sys/arch/riscv/starfive/files.starfive:1.5
--- src/sys/arch/riscv/starfive/files.starfive:1.4 Sat Jul 27 07:09:50 2024
+++ src/sys/arch/riscv/starfive/files.starfive Sat Oct 26 15:49:43 2024
@@ -1,4 +1,4 @@
-# $NetBSD: files.starfive,v 1.4 2024/07/27 07:09:50 skrll Exp $
+# $NetBSD: files.starfive,v 1.5 2024/10/26 15:49:43 skrll Exp $
#
# Configuration info for StarFive SoCs
#
@@ -23,3 +23,14 @@ file arch/riscv/starfive/jh71x0_usb.c j
device jh7100pinctrl
attach jh7100pinctrl at fdt with jh7100_pinctrl
file arch/riscv/starfive/jh7100_pinctrl.c jh7100_pinctrl
+
+# Ethernet
+# JH7100 GMAC
+attach awge at fdt with jh7100_gmac
+
+# JH7110 EOQS
+attach eqos at fdt with jh7110_eqos
+
+file arch/riscv/starfive/jh7100_gmac.c jh7100_gmac
+file arch/riscv/starfive/jh7110_eqos.c jh7110_eqos
+file arch/riscv/starfive/jh71x0_eth.c jh7100_gmac | jh7110_eqos
Added files:
Index: src/sys/arch/riscv/starfive/jh7100_gmac.c
diff -u /dev/null src/sys/arch/riscv/starfive/jh7100_gmac.c:1.1
--- /dev/null Sat Oct 26 15:49:43 2024
+++ src/sys/arch/riscv/starfive/jh7100_gmac.c Sat Oct 26 15:49:43 2024
@@ -0,0 +1,160 @@
+/* $NetBSD: jh7100_gmac.c,v 1.1 2024/10/26 15:49:43 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: jh7100_gmac.c,v 1.1 2024/10/26 15:49:43 skrll Exp $");
+
+#include <sys/param.h>
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/rndsource.h>
+
+#include <net/if_ether.h>
+#include <net/if_media.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/dwc_gmac_var.h>
+#include <dev/ic/dwc_gmac_reg.h>
+
+#include <prop/proplib.h>
+
+#include <riscv/starfive/jh71x0_eth.h>
+
+struct jh7100_gmac_softc {
+ struct dwc_gmac_softc sc_gmac;
+ struct jh71x0_eth_softc sc_jh71x0eth;
+};
+
+static void
+jh7100_gmac_set_speed(struct dwc_gmac_softc *gmac_sc, int speed)
+{
+ struct jh7100_gmac_softc * const sc =
+ container_of(gmac_sc, struct jh7100_gmac_softc, sc_gmac);
+ struct jh71x0_eth_softc * const jheth_sc = &sc->sc_jh71x0eth;
+
+ u_int rate = clk_get_rate(jheth_sc->sc_clk_tx);
+ switch (speed) {
+ case IFM_10_T:
+ rate = 2500000;
+ break;
+ case IFM_100_TX:
+ rate = 25000000;
+ break;
+ case IFM_1000_T:
+ rate = 125000000;
+ default:
+ // error unsupported
+ break;
+ }
+
+ int error = clk_set_rate(jheth_sc->sc_clk_tx, rate);
+ if (error)
+ aprint_error_dev(jheth_sc->sc_dev, "failed to set TX rate %u",
+ rate);
+}
+
+static int
+jh7100_gmac_intr(void *arg)
+{
+ return dwc_gmac_intr(arg);
+}
+
+/* Compat string(s) */
+static const struct device_compatible_entry compat_data[] = {
+ { .compat = "starfive,jh7100-dwmac" },
+ DEVICE_COMPAT_EOL
+};
+
+static int
+jh7100_gmac_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_compatible_match(faa->faa_phandle, compat_data);
+}
+
+static void
+jh7100_gmac_attach(device_t parent, device_t self, void *aux)
+{
+ struct jh7100_gmac_softc * const sc = device_private(self);
+ struct jh71x0_eth_softc * const jheth_sc = &sc->sc_jh71x0eth;
+ struct dwc_gmac_softc * const gmac_sc = &sc->sc_gmac;
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ char intrstr[128];
+ int error;
+
+ sc->sc_gmac.sc_dev = self;
+ sc->sc_gmac.sc_bst = faa->faa_bst;
+ sc->sc_gmac.sc_dmat = faa->faa_dmat;
+ sc->sc_jh71x0eth.sc_dev = self;
+ sc->sc_jh71x0eth.sc_phy = MII_PHY_ANY;
+ sc->sc_jh71x0eth.sc_type = JH71X0ETH_GMAC;
+
+ error = jh71x0_eth_attach(jheth_sc, faa, &sc->sc_gmac.sc_bsh);
+ if (error)
+ return;
+
+ if (sc->sc_jh71x0eth.sc_clk_tx) {
+ sc->sc_gmac.sc_set_speed = jh7100_gmac_set_speed;
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": Gigabit Ethernet Controller\n");
+
+ error = dwc_gmac_attach(gmac_sc, sc->sc_jh71x0eth.sc_phy,
+ GMAC_MII_CLK_150_250M_DIV102);
+ if (error)
+ return;
+
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error(": failed to decode interrupt\n");
+ return;
+ }
+ void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET,
+ FDT_INTR_MPSAFE, jh7100_gmac_intr, sc, device_xname(self));
+ if (ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt on %s\n",
+ intrstr);
+ // XXXNH unwind
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+}
+
+
+CFATTACH_DECL_NEW(jh7100_gmac, sizeof(struct jh7100_gmac_softc),
+ jh7100_gmac_match, jh7100_gmac_attach, NULL, NULL);
Index: src/sys/arch/riscv/starfive/jh7110_eqos.c
diff -u /dev/null src/sys/arch/riscv/starfive/jh7110_eqos.c:1.1
--- /dev/null Sat Oct 26 15:49:43 2024
+++ src/sys/arch/riscv/starfive/jh7110_eqos.c Sat Oct 26 15:49:43 2024
@@ -0,0 +1,167 @@
+/* $NetBSD: jh7110_eqos.c,v 1.1 2024/10/26 15:49:43 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: jh7110_eqos.c,v 1.1 2024/10/26 15:49:43 skrll Exp $");
+
+#include <sys/param.h>
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/rndsource.h>
+
+#include <net/if_ether.h>
+#include <net/if_media.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <dev/fdt/syscon.h> // maybe not
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/dwc_eqos_var.h>
+
+#include <prop/proplib.h>
+
+#include <riscv/starfive/jh71x0_eth.h>
+
+
+
+
+struct jh7110_eqos_softc {
+ struct eqos_softc sc_eqos;
+ struct jh71x0_eth_softc sc_jh71x0eth;
+};
+
+static void
+jh7110_parse_phyprops(struct jh7110_eqos_softc *jh_sc, int phandle)
+{
+ struct eqos_softc * const sc = &jh_sc->sc_eqos;
+ prop_dictionary_t dict = device_properties(sc->sc_dev);
+
+ if (of_hasprop(phandle, "motorcomm,tx-clk-adj-enabled")) {
+ prop_dictionary_set_bool(dict, "motorcomm,tx-clk-adj-enabled",
+ true);
+ }
+ if (of_hasprop(phandle, "motorcomm,tx-clk-100-inverted")) {
+ prop_dictionary_set_bool(dict, "motorcomm,tx-clk-100-inverted",
+ true);
+ }
+ if (of_hasprop(phandle, "motorcomm,tx-clk-1000-inverted")) {
+ prop_dictionary_set_bool(dict, "motorcomm,tx-clk-1000-inverted",
+ true);
+ }
+
+ uint32_t val;
+ if (of_getprop_uint32(phandle,
+ "motorcomm,rx-clk-drv-microamp", &val) == 0) {
+ prop_dictionary_set_uint32(dict,
+ "motorcomm,rx-clk-drv-microamp", val);
+ }
+ if (of_getprop_uint32(phandle,
+ "motorcomm,rx-data-drv-microamp", &val) == 0) {
+ prop_dictionary_set_uint32(dict,
+ "motorcomm,rx-data-drv-microamp", val);
+ }
+ if (of_getprop_uint32(phandle,
+ "rx-internal-delay-ps", &val) == 0) {
+ prop_dictionary_set_uint32(dict,
+ "rx-internal-delay-ps", val);
+ }
+ if (of_getprop_uint32(phandle,
+ "tx-internal-delay-ps", &val) == 0) {
+ prop_dictionary_set_uint32(dict,
+ "tx-internal-delay-ps", val);
+ }
+}
+
+/* Compat string(s) */
+static const struct device_compatible_entry compat_data[] = {
+ { .compat = "starfive,jh7110-dwmac" },
+ DEVICE_COMPAT_EOL
+};
+
+static int
+jh7110_eqos_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_compatible_match(faa->faa_phandle, compat_data);
+}
+static void
+jh7110_eqos_attach(device_t parent, device_t self, void *aux)
+{
+ struct jh7110_eqos_softc * const sc = device_private(self);
+ struct jh71x0_eth_softc * const jheth_sc = &sc->sc_jh71x0eth;
+ struct eqos_softc * const eqos_sc = &sc->sc_eqos;
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ char intrstr[128];
+ int error;
+
+ sc->sc_eqos.sc_dev = self;
+ sc->sc_eqos.sc_bst = faa->faa_bst;
+ sc->sc_eqos.sc_dmat = faa->faa_dmat;
+ sc->sc_jh71x0eth.sc_dev = self;
+ sc->sc_jh71x0eth.sc_phy = MII_PHY_ANY;
+ sc->sc_jh71x0eth.sc_type = JH71X0ETH_EQOS;
+
+ error = jh71x0_eth_attach(jheth_sc, faa, &sc->sc_eqos.sc_bsh);
+ if (error)
+ return;
+
+ jh7110_parse_phyprops(sc, sc->sc_jh71x0eth.sc_phandle_phy);
+
+// aprint_naive("\n");
+// aprint_normal(": Gigabit Ethernet Controller\n");
+
+#define CSR_RATE_RGMII 125000000 /* default */
+ eqos_sc->sc_csr_clock = CSR_RATE_RGMII;
+ error = eqos_attach(eqos_sc);
+ if (error)
+ return;
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error(": failed to decode interrupt\n");
+ return;
+ }
+ void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET,
+ FDT_INTR_MPSAFE, eqos_intr, eqos_sc, device_xname(self));
+ if (ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt on %s\n",
+ intrstr);
+ // XXXNH unwind
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+}
+
+CFATTACH_DECL_NEW(jh7110_eqos, sizeof(struct jh7110_eqos_softc),
+ jh7110_eqos_match, jh7110_eqos_attach, NULL, NULL);
Index: src/sys/arch/riscv/starfive/jh71x0_eth.c
diff -u /dev/null src/sys/arch/riscv/starfive/jh71x0_eth.c:1.1
--- /dev/null Sat Oct 26 15:49:43 2024
+++ src/sys/arch/riscv/starfive/jh71x0_eth.c Sat Oct 26 15:49:43 2024
@@ -0,0 +1,179 @@
+/* $NetBSD: jh71x0_eth.c,v 1.1 2024/10/26 15:49:43 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: jh71x0_eth.c,v 1.1 2024/10/26 15:49:43 skrll Exp $");
+
+#include <sys/param.h>
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/rndsource.h>
+
+#include <net/if_ether.h>
+#include <net/if_media.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <dev/fdt/syscon.h>
+
+#include <dev/mii/miivar.h>
+
+//#include <prop/proplib.h>
+
+#include <riscv/starfive/jh71x0_eth.h>
+
+
+/* Register definitions */
+
+#define STARFIVE_GMAC_PHY_INFT_RGMII 0x1
+#define STARFIVE_GMAC_PHY_INFT_RMII 0x4
+#define STARFIVE_GMAC_PHY_INFT_MASK __BITS(2, 0)
+
+#define JH7100_SYSMAIN_REGISTER49_DLYCHAIN 0xc8
+
+static void
+jh71x0_eth_set_phy_rgmii_id(struct jh71x0_eth_softc *jh_sc)
+{
+ const uint32_t reg = jh_sc->sc_phy_syscon_reg;
+ const uint32_t shift = jh_sc->sc_phy_syscon_shift;
+
+ syscon_lock(jh_sc->sc_syscon);
+ uint32_t val = syscon_read_4(jh_sc->sc_syscon, reg);
+ val &= ~(STARFIVE_GMAC_PHY_INFT_MASK << shift);
+ val |= STARFIVE_GMAC_PHY_INFT_RGMII << shift;
+ syscon_write_4(jh_sc->sc_syscon, reg, val);
+
+ if (jh_sc->sc_type == JH71X0ETH_GMAC) {
+ syscon_write_4(jh_sc->sc_syscon,
+ JH7100_SYSMAIN_REGISTER49_DLYCHAIN, 4);
+ }
+
+ syscon_unlock(jh_sc->sc_syscon);
+}
+
+
+int
+jh71x0_eth_attach(struct jh71x0_eth_softc *jh_sc, struct fdt_attach_args *faa,
+ bus_space_handle_t *bshp)
+{
+ const int phandle = faa->faa_phandle;
+ int phandle_phy;
+ bus_addr_t addr;
+ bus_size_t size;
+ int error;
+ int n;
+
+ error = fdtbus_get_reg(phandle, 0, &addr, &size);
+ if (error) {
+ aprint_error(": couldn't get registers\n");
+ return ENXIO;
+ }
+
+ int len;
+ const u_int * const syscon_data =
+ fdtbus_get_prop(phandle, "starfive,syscon", &len);
+ if (syscon_data == NULL) {
+ aprint_error(": couldn't get 'starfive,syscon' property\n");
+ return ENXIO;
+ }
+ if (len != 3 * sizeof(uint32_t)) {
+ aprint_error(": incorrect syscon data (len = %u)\n",
+ len);
+ return ENXIO;
+ }
+
+ const int syscon_phandle =
+ fdtbus_get_phandle_from_native(be32dec(&syscon_data[0]));
+
+ jh_sc->sc_syscon = fdtbus_syscon_lookup(syscon_phandle);
+ if (jh_sc->sc_syscon == NULL) {
+ aprint_error(": couldn't get syscon\n");
+ return ENXIO;
+ }
+
+ jh_sc->sc_phy_syscon_reg = be32dec(&syscon_data[1]);
+ jh_sc->sc_phy_syscon_shift = be32dec(&syscon_data[2]);
+
+ if (bus_space_map(faa->faa_bst, addr, size, 0, bshp) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return ENXIO;
+ }
+
+ /* enable clocks */
+ struct clk *clk;
+ fdtbus_clock_assign(phandle);
+ for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) {
+ if (clk_enable(clk) != 0) {
+ aprint_error(": couldn't enable clock #%d\n", n);
+ return ENXIO;
+ }
+ }
+ /* de-assert resets */
+ struct fdtbus_reset *rst;
+ for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) {
+ if (fdtbus_reset_deassert(rst) != 0) {
+ aprint_error(": couldn't de-assert reset #%d\n", n);
+ return ENXIO;
+ }
+ }
+
+ const char *phy_mode = fdtbus_get_string(phandle, "phy-mode");
+ if (phy_mode == NULL)
+ phy_mode = "rgmii-id"; /* default: RGMII */
+
+ phandle_phy = fdtbus_get_phandle(phandle, "phy-handle");
+ if (phandle_phy > 0) {
+ of_getprop_uint32(phandle_phy, "reg", &jh_sc->sc_phy);
+ }
+ jh_sc->sc_phandle_phy = phandle_phy;
+
+ if (strncmp(phy_mode, "rgmii-id", 8) == 0) {
+ jh71x0_eth_set_phy_rgmii_id(jh_sc);
+ } else {
+ aprint_error(": unsupported phy-mode '%s'\n", phy_mode);
+ return ENXIO;
+ }
+
+ if (!of_hasprop(phandle, "starfive,tx-use-rgmii-clk")) {
+ jh_sc->sc_clk_tx = fdtbus_clock_get(phandle, "tx");
+ }
+
+ const uint8_t *macaddr = fdtbus_get_prop(phandle, "local-mac-address",
+ &len);
+ if (macaddr != NULL && len == ETHER_ADDR_LEN) {
+ prop_dictionary_t prop = device_properties(jh_sc->sc_dev);
+ prop_dictionary_set_data(prop, "mac-address", macaddr, len);
+ }
+
+ return 0;
+}
+
Index: src/sys/arch/riscv/starfive/jh71x0_eth.h
diff -u /dev/null src/sys/arch/riscv/starfive/jh71x0_eth.h:1.1
--- /dev/null Sat Oct 26 15:49:43 2024
+++ src/sys/arch/riscv/starfive/jh71x0_eth.h Sat Oct 26 15:49:43 2024
@@ -0,0 +1,59 @@
+/* $NetBSD: jh71x0_eth.h,v 1.1 2024/10/26 15:49:43 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2024 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _STARFIVE_JH71X0ETH_H
+#define _STARFIVE_JH71X0ETH_H
+
+enum jh7x10_eth_type {
+ JH71X0ETH_GMAC,
+ JH71X0ETH_EQOS,
+};
+
+
+struct jh71x0_eth_softc {
+ enum jh7x10_eth_type sc_type;
+ device_t sc_dev;
+
+ struct syscon * sc_syscon;
+ uint32_t sc_phy_syscon_reg;
+ uint32_t sc_phy_syscon_shift;
+
+ int sc_phandle_phy;
+ int sc_phy;
+
+ struct clk * sc_clk_tx;
+};
+
+
+int jh71x0_eth_attach(struct jh71x0_eth_softc *, struct fdt_attach_args *,
+ bus_space_handle_t *);
+
+#endif
