Module Name: src
Committed By: nat
Date: Sat Oct 26 20:53:08 UTC 2024
Modified Files:
src/sys/arch/mac68k/dev: sbc.c
Log Message:
Rework of previous.
While here set the priority in sync witho pdma_in/out.
Use sbc_ready same as pdma_in/out.
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mac68k/dev/sbc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mac68k/dev/sbc.c
diff -u src/sys/arch/mac68k/dev/sbc.c:1.60 src/sys/arch/mac68k/dev/sbc.c:1.61
--- src/sys/arch/mac68k/dev/sbc.c:1.60 Sat Sep 14 21:11:07 2024
+++ src/sys/arch/mac68k/dev/sbc.c Sat Oct 26 20:53:07 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: sbc.c,v 1.60 2024/09/14 21:11:07 nat Exp $ */
+/* $NetBSD: sbc.c,v 1.61 2024/10/26 20:53:07 nat Exp $ */
/*
* Copyright (C) 1996 Scott Reynolds. All rights reserved.
@@ -45,7 +45,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.60 2024/09/14 21:11:07 nat Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sbc.c,v 1.61 2024/10/26 20:53:07 nat Exp $");
#include "opt_ddb.h"
@@ -430,12 +430,12 @@ sbc_drq_intr(void *p)
u_int32_t *long_data;
volatile u_int8_t *drq = 0; /* XXX gcc4 -Wuninitialized */
u_int8_t *data;
- int block, count, dcount, resid;
+ int count, dcount, s;
/*
* If we're not ready to xfer data, or have no more, just return.
*/
- if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0 || dh->dh_len == 0)
+ if (sbc_ready(ncr_sc) || dh->dh_len == 0)
return;
#ifdef SBC_DEBUG
@@ -443,6 +443,7 @@ sbc_drq_intr(void *p)
printf("%s: drq intr, dh_len=0x%x, dh_flags=0x%x\n",
device_xname(ncr_sc->sc_dev), dh->dh_len, dh->dh_flags);
#endif
+ s = splbio();
/*
* Setup for a possible bus error caused by SCSI controller
@@ -451,6 +452,7 @@ sbc_drq_intr(void *p)
*/
nofault = &faultbuf;
+ m68k_fault_addr = 0;
if (setjmp(nofault)) {
nofault = (label_t *)0;
if ((dh->dh_flags & SBC_DH_DONE) == 0) {
@@ -476,60 +478,61 @@ sbc_drq_intr(void *p)
#endif
m68k_fault_addr = 0;
+ splx(s);
+
return;
}
+#define CHECKMORE if (sbc_ready(ncr_sc)) { \
+ dh->dh_len -= dcount - count; \
+ dh->dh_addr += dcount - count; \
+ if (dh->dh_len) \
+ goto no_more; \
+ }
+
if (dh->dh_flags & SBC_DH_OUT) { /* Data Out */
dcount = 0;
/*
* Get the source address aligned.
*/
- resid =
+ dcount =
count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3));
if (count && count < 4) {
drq = (volatile u_int8_t *)sc->sc_drq_addr;
data = (u_int8_t *)dh->dh_addr;
-#define W1 *drq++ = *data++
+#define W1 CHECKMORE *drq++ = *data++
while (count) {
W1; count--;
}
#undef W1
- dh->dh_addr += resid;
- dh->dh_len -= resid;
+ dh->dh_addr += dcount;
+ dh->dh_len -= dcount;
}
/*
* Start the transfer.
*/
while (dh->dh_len) {
- if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0)
- goto no_more;
-
- block = 512;
- if (resid && resid != 4)
- block -= 4;
- resid = 0;
+#define W4 CHECKMORE *long_drq++ = *long_data++; count -= 4
- dcount = count = uimin(dh->dh_len, block);
+ dcount = count = uimin(dh->dh_len, MAX_DMA_LEN);
long_drq = (volatile u_int32_t *)sc->sc_drq_addr;
long_data = (u_int32_t *)dh->dh_addr;
-#define W4 *long_drq++ = *long_data++
while (count >= 64) {
W4; W4; W4; W4; W4; W4; W4; W4;
W4; W4; W4; W4; W4; W4; W4; W4; /* 64 */
- count -= 64;
}
while (count >= 4) {
- W4; count -= 4;
+ W4;
}
#undef W4
data = (u_int8_t *)long_data;
drq = (volatile u_int8_t *)long_drq;
-#define W1 *drq++ = *data++
+#define W1 CHECKMORE *drq++ = *data++
while (count) {
W1; count--;
}
@@ -538,6 +541,8 @@ sbc_drq_intr(void *p)
dh->dh_addr += dcount;
}
dh->dh_flags |= SBC_DH_DONE;
+ if (dcount >= MAX_DMA_LEN)
+ drq = (volatile u_int8_t *)sc->sc_drq_addr;
/*
* XXX -- Read a byte from the SBC to trigger a /BERR.
@@ -549,49 +554,40 @@ sbc_drq_intr(void *p)
/*
* Get the dest address aligned.
*/
- resid =
+ dcount =
count = uimin(dh->dh_len, 4 - (((int)dh->dh_addr) & 0x3));
if (count && count < 4) {
data = (u_int8_t *)dh->dh_addr;
drq = (volatile u_int8_t *)sc->sc_drq_addr;
while (count) {
- *data++ = *drq++;
+ CHECKMORE *data++ = *drq++;
count--;
}
- dh->dh_addr += resid;
- dh->dh_len -= resid;
+ dh->dh_addr += dcount;
+ dh->dh_len -= dcount;
}
/*
* Start the transfer.
*/
while (dh->dh_len) {
- if ((*ncr_sc->sci_csr & SCI_CSR_DREQ) == 0)
- goto no_more;
-
- block = 512;
- if (resid && resid != 4)
- block -= 4;
- resid = 0;
-
- dcount = count = uimin(dh->dh_len, block);
+ dcount = count = uimin(dh->dh_len, MAX_DMA_LEN);
long_data = (u_int32_t *)dh->dh_addr;
long_drq = (volatile u_int32_t *)sc->sc_drq_addr;
-#define R4 *long_data++ = *long_drq++
+#define R4 CHECKMORE *long_data++ = *long_drq++; count -= 4
while (count >= 64) {
R4; R4; R4; R4; R4; R4; R4; R4;
R4; R4; R4; R4; R4; R4; R4; R4; /* 64 */
- count -= 64;
}
while (count >= 4) {
- R4; count -= 4;
+ R4;
}
#undef R4
data = (u_int8_t *)long_data;
drq = (volatile u_int8_t *)long_drq;
while (count) {
- *data++ = *drq++;
+ CHECKMORE *data++ = *drq++;
count--;
}
dh->dh_len -= dcount;
@@ -599,6 +595,7 @@ sbc_drq_intr(void *p)
}
dh->dh_flags |= SBC_DH_DONE;
}
+#undef CHECKMORE
no_more:
/*
@@ -607,6 +604,8 @@ no_more:
*/
nofault = (label_t *)0;
+ splx(s);
+
#ifdef SBC_DEBUG
if (sbc_debug & (SBC_DB_REG | SBC_DB_INTR))
printf("%s: drq intr complete: csr=0x%x, bus_csr=0x%x\n",
