Module Name: src
Committed By: andvar
Date: Sun Dec 8 06:55:52 UTC 2024
Modified Files:
src/sys/arch/m68k/fpsp: x_operr.sa
Log Message:
s/erroneoulsy/erroneously/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/m68k/fpsp/x_operr.sa
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/m68k/fpsp/x_operr.sa
diff -u src/sys/arch/m68k/fpsp/x_operr.sa:1.5 src/sys/arch/m68k/fpsp/x_operr.sa:1.6
--- src/sys/arch/m68k/fpsp/x_operr.sa:1.5 Sun Sep 16 16:34:32 2001
+++ src/sys/arch/m68k/fpsp/x_operr.sa Sun Dec 8 06:55:52 2024
@@ -1,4 +1,4 @@
-* $NetBSD: x_operr.sa,v 1.5 2001/09/16 16:34:32 wiz Exp $
+* $NetBSD: x_operr.sa,v 1.6 2024/12/08 06:55:52 andvar Exp $
* MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
* M68000 Hi-Performance Microprocessor Division
@@ -57,7 +57,7 @@
*
* where exp = (true exp) - 1
*
-* So, wbtemp and fptemp will contain the following on erroneoulsy
+* So, wbtemp and fptemp will contain the following on erroneously
* signalled operr:
* fpts = 1
* fpte = $4000 (15 bit externally)
