Module Name: src Committed By: andvar Date: Tue Jan 7 20:14:52 UTC 2025
Modified Files:
src/sys/arch/alpha/pci: pci_swiz_bus_mem_chipdep.c
Log Message:
s/prefectchable/prefetchable/ in variable name, messages and comments.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50 src/sys/arch/alpha/pci/pci_swiz_bus_mem_chipdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
