Module Name: src
Committed By: nonaka
Date: Thu Apr 30 05:19:38 UTC 2009
Modified Files:
src/sys/arch/sh3/include: scireg.h
Log Message:
Added some register definition.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/sh3/include/scireg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/sh3/include/scireg.h
diff -u src/sys/arch/sh3/include/scireg.h:1.8 src/sys/arch/sh3/include/scireg.h:1.9
--- src/sys/arch/sh3/include/scireg.h:1.8 Tue Jul 1 11:49:37 2003
+++ src/sys/arch/sh3/include/scireg.h Thu Apr 30 05:19:38 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: scireg.h,v 1.8 2003/07/01 11:49:37 uwe Exp $ */
+/* $NetBSD: scireg.h,v 1.9 2009/04/30 05:19:38 nonaka Exp $ */
/*-
* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
@@ -43,6 +43,7 @@
#define SHREG_SCTDR (*(volatile unsigned char *) 0xFFFFFE86)
#define SHREG_SCSSR (*(volatile unsigned char *) 0xFFFFFE88)
#define SHREG_SCRDR (*(volatile unsigned char *) 0xFFFFFE8A)
+#define SHREG_SCSCMR (*(volatile unsigned char *) 0xFFFFFE8C)
#define SHREG_SCSPDR (*(volatile unsigned char *) 0xf4000136)
#else
@@ -59,6 +60,15 @@
#endif
+#define SCSMR_CA 0x80
+#define SCSMR_CHR 0x40
+#define SCSMR_PE 0x20
+#define SCSMR_OE 0x10
+#define SCSMR_STOP 0x08
+#define SCSMR_MP 0x04
+#define SCSMR_CKS1 0x02
+#define SCSMR_CKS0 0x01
+
#define SCSCR_TIE 0x80 /* Transmit Interrupt Enable */
#define SCSCR_RIE 0x40 /* Receive Interrupt Enable */
#define SCSCR_TE 0x20 /* Transmit Enable */
@@ -73,6 +83,9 @@
#define SCSSR_ORER 0x20
#define SCSSR_FER 0x10
#define SCSSR_PER 0x08
+#define SCSSR_TEND 0x04
+#define SCSSR_MPB 0x02
+#define SCSSR_MPBT 0x01
#define SCSPTR_SPB1IO 0x08
#define SCSPTR_SPB1DT 0x04
