Module Name: src
Committed By: mjf
Date: Sun May 17 18:21:29 UTC 2009
Modified Files:
src/sys/arch/hp700/hp700: pim.h
Log Message:
u_intNN_t -> uintNN_t
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/hp700/hp700/pim.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/hp700/hp700/pim.h
diff -u src/sys/arch/hp700/hp700/pim.h:1.3 src/sys/arch/hp700/hp700/pim.h:1.4
--- src/sys/arch/hp700/hp700/pim.h:1.3 Sat May 16 16:06:06 2009
+++ src/sys/arch/hp700/hp700/pim.h Sun May 17 18:21:29 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: pim.h,v 1.3 2009/05/16 16:06:06 mjf Exp $ */
+/* $NetBSD: pim.h,v 1.4 2009/05/17 18:21:29 mjf Exp $ */
/*-
* Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -45,93 +45,93 @@
struct hp700_pim_regs {
/* The general registers. */
- u_int pim_regs_r0;
- u_int pim_regs_r1;
- u_int pim_regs_r2;
- u_int pim_regs_r3;
- u_int pim_regs_r4;
- u_int pim_regs_r5;
- u_int pim_regs_r6;
- u_int pim_regs_r7;
- u_int pim_regs_r8;
- u_int pim_regs_r9;
- u_int pim_regs_r10;
- u_int pim_regs_r11;
- u_int pim_regs_r12;
- u_int pim_regs_r13;
- u_int pim_regs_r14;
- u_int pim_regs_r15;
- u_int pim_regs_r16;
- u_int pim_regs_r17;
- u_int pim_regs_r18;
- u_int pim_regs_r19;
- u_int pim_regs_r20;
- u_int pim_regs_r21;
- u_int pim_regs_r22;
- u_int pim_regs_r23;
- u_int pim_regs_r24;
- u_int pim_regs_r25;
- u_int pim_regs_r26;
- u_int pim_regs_r27;
- u_int pim_regs_r28;
- u_int pim_regs_r29;
- u_int pim_regs_r30;
- u_int pim_regs_r31;
+ uint32_t pim_regs_r0;
+ uint32_t pim_regs_r1;
+ uint32_t pim_regs_r2;
+ uint32_t pim_regs_r3;
+ uint32_t pim_regs_r4;
+ uint32_t pim_regs_r5;
+ uint32_t pim_regs_r6;
+ uint32_t pim_regs_r7;
+ uint32_t pim_regs_r8;
+ uint32_t pim_regs_r9;
+ uint32_t pim_regs_r10;
+ uint32_t pim_regs_r11;
+ uint32_t pim_regs_r12;
+ uint32_t pim_regs_r13;
+ uint32_t pim_regs_r14;
+ uint32_t pim_regs_r15;
+ uint32_t pim_regs_r16;
+ uint32_t pim_regs_r17;
+ uint32_t pim_regs_r18;
+ uint32_t pim_regs_r19;
+ uint32_t pim_regs_r20;
+ uint32_t pim_regs_r21;
+ uint32_t pim_regs_r22;
+ uint32_t pim_regs_r23;
+ uint32_t pim_regs_r24;
+ uint32_t pim_regs_r25;
+ uint32_t pim_regs_r26;
+ uint32_t pim_regs_r27;
+ uint32_t pim_regs_r28;
+ uint32_t pim_regs_r29;
+ uint32_t pim_regs_r30;
+ uint32_t pim_regs_r31;
/* The control registers. */
- u_int pim_regs_cr0;
- u_int pim_regs_cr1;
- u_int pim_regs_cr2;
- u_int pim_regs_cr3;
- u_int pim_regs_cr4;
- u_int pim_regs_cr5;
- u_int pim_regs_cr6;
- u_int pim_regs_cr7;
- u_int pim_regs_cr8;
- u_int pim_regs_cr9;
- u_int pim_regs_cr10;
- u_int pim_regs_cr11;
- u_int pim_regs_cr12;
- u_int pim_regs_cr13;
- u_int pim_regs_cr14;
- u_int pim_regs_cr15;
- u_int pim_regs_cr16;
- u_int pim_regs_cr17;
- u_int pim_regs_cr18;
- u_int pim_regs_cr19;
- u_int pim_regs_cr20;
- u_int pim_regs_cr21;
- u_int pim_regs_cr22;
- u_int pim_regs_cr23;
- u_int pim_regs_cr24;
- u_int pim_regs_cr25;
- u_int pim_regs_cr26;
- u_int pim_regs_cr27;
- u_int pim_regs_cr28;
- u_int pim_regs_cr29;
- u_int pim_regs_cr30;
- u_int pim_regs_cr31;
+ uint32_t pim_regs_cr0;
+ uint32_t pim_regs_cr1;
+ uint32_t pim_regs_cr2;
+ uint32_t pim_regs_cr3;
+ uint32_t pim_regs_cr4;
+ uint32_t pim_regs_cr5;
+ uint32_t pim_regs_cr6;
+ uint32_t pim_regs_cr7;
+ uint32_t pim_regs_cr8;
+ uint32_t pim_regs_cr9;
+ uint32_t pim_regs_cr10;
+ uint32_t pim_regs_cr11;
+ uint32_t pim_regs_cr12;
+ uint32_t pim_regs_cr13;
+ uint32_t pim_regs_cr14;
+ uint32_t pim_regs_cr15;
+ uint32_t pim_regs_cr16;
+ uint32_t pim_regs_cr17;
+ uint32_t pim_regs_cr18;
+ uint32_t pim_regs_cr19;
+ uint32_t pim_regs_cr20;
+ uint32_t pim_regs_cr21;
+ uint32_t pim_regs_cr22;
+ uint32_t pim_regs_cr23;
+ uint32_t pim_regs_cr24;
+ uint32_t pim_regs_cr25;
+ uint32_t pim_regs_cr26;
+ uint32_t pim_regs_cr27;
+ uint32_t pim_regs_cr28;
+ uint32_t pim_regs_cr29;
+ uint32_t pim_regs_cr30;
+ uint32_t pim_regs_cr31;
/* The space registers. */
- u_int pim_regs_sr0;
- u_int pim_regs_sr1;
- u_int pim_regs_sr2;
- u_int pim_regs_sr3;
- u_int pim_regs_sr4;
- u_int pim_regs_sr5;
- u_int pim_regs_sr6;
- u_int pim_regs_sr7;
+ uint32_t pim_regs_sr0;
+ uint32_t pim_regs_sr1;
+ uint32_t pim_regs_sr2;
+ uint32_t pim_regs_sr3;
+ uint32_t pim_regs_sr4;
+ uint32_t pim_regs_sr5;
+ uint32_t pim_regs_sr6;
+ uint32_t pim_regs_sr7;
/* The back entries of the instruction address queues. */
- u_int pim_regs_iisq_tail;
- u_int pim_regs_iioq_tail;
+ uint32_t pim_regs_iisq_tail;
+ uint32_t pim_regs_iioq_tail;
};
/* The PIM data for HPMC and LPMC contains this check information. */
struct hp700_pim_checks {
/* The Check Type. */
- u_int pim_check_type;
+ uint32_t pim_check_type;
#define PIM_CHECK_CACHE (1 << 31)
#define PIM_CHECK_TLB (1 << 30)
#define PIM_CHECK_BUS (1 << 29)
@@ -142,7 +142,7 @@
* The CPU State. In addition to the common PIM_CPU_
* bits defined below, some fields are HPMC-specific.
*/
- u_int pim_check_cpu_state;
+ uint32_t pim_check_cpu_state;
#define PIM_CPU_IQV (1 << 31)
#define PIM_CPU_IQF (1 << 30)
#define PIM_CPU_IPV (1 << 29)
@@ -157,10 +157,10 @@
#define PIM_CPU_HPMC_CS(cs) ((cs) & 0x3)
#define PIM_CPU_HPMC_BITS PIM_CPU_BITS "\004HD\003SIS"
- u_int pim_check_reserved_0;
+ uint32_t pim_check_reserved_0;
/* The Cache Check word. */
- u_int pim_check_cache;
+ uint32_t pim_check_cache;
#define PIM_CACHE_ICC (1 << 31)
#define PIM_CACHE_DCC (1 << 30)
#define PIM_CACHE_TC (1 << 29)
@@ -172,7 +172,7 @@
#define PIM_CACHE_BITS "\020\040ICC\037DCC\036TC\035DC\034CRG\033LC\032RCC"
/* The TLB Check word. */
- u_int pim_check_tlb;
+ uint32_t pim_check_tlb;
#define PIM_TLB_ITC (1 << 31)
#define PIM_TLB_DTC (1 << 30)
#define PIM_TLB_TRG (1 << 29)
@@ -181,7 +181,7 @@
#define PIM_TLB_BITS "\020\040ITC\037DTC\036TRG\035TUC\034TNF"
/* The Bus Check word. */
- u_int pim_check_bus;
+ uint32_t pim_check_bus;
#define PIM_BUS_RSV (1 << 21)
#define PIM_BUS_RQV (1 << 20)
#define PIM_BUS_VAR(bc) (((bc) >> 16) & 0xf)
@@ -193,56 +193,56 @@
#define PIM_BUS_BITS "\020\026RSV\025RQV\010PIV\007BSV"
/* The Assist Check word. */
- u_int pim_check_assist;
+ uint32_t pim_check_assist;
#define PIM_ASSIST_COC (1 << 31)
#define PIM_ASSIST_SC (1 << 30)
#define PIM_ASSIST_BITS "\020\040COC\037SC"
- u_int pim_check_reserved_1;
+ uint32_t pim_check_reserved_1;
/* Additional information about the check. */
- u_int pim_check_assist_state;
- u_int pim_check_responder;
- u_int pim_check_requestor;
- u_int pim_check_path_info;
+ uint32_t pim_check_assist_state;
+ uint32_t pim_check_responder;
+ uint32_t pim_check_requestor;
+ uint32_t pim_check_path_info;
};
/* The PIM data for HPMC and LPMC contains this register array. */
struct hp700_pim_fpregs {
/* The FPU state. */
- u_int64_t pim_fpregs_fp0;
- u_int64_t pim_fpregs_fp1;
- u_int64_t pim_fpregs_fp2;
- u_int64_t pim_fpregs_fp3;
- u_int64_t pim_fpregs_fp4;
- u_int64_t pim_fpregs_fp5;
- u_int64_t pim_fpregs_fp6;
- u_int64_t pim_fpregs_fp7;
- u_int64_t pim_fpregs_fp8;
- u_int64_t pim_fpregs_fp9;
- u_int64_t pim_fpregs_fp10;
- u_int64_t pim_fpregs_fp11;
- u_int64_t pim_fpregs_fp12;
- u_int64_t pim_fpregs_fp13;
- u_int64_t pim_fpregs_fp14;
- u_int64_t pim_fpregs_fp15;
- u_int64_t pim_fpregs_fp16;
- u_int64_t pim_fpregs_fp17;
- u_int64_t pim_fpregs_fp18;
- u_int64_t pim_fpregs_fp19;
- u_int64_t pim_fpregs_fp20;
- u_int64_t pim_fpregs_fp21;
- u_int64_t pim_fpregs_fp22;
- u_int64_t pim_fpregs_fp23;
- u_int64_t pim_fpregs_fp24;
- u_int64_t pim_fpregs_fp25;
- u_int64_t pim_fpregs_fp26;
- u_int64_t pim_fpregs_fp27;
- u_int64_t pim_fpregs_fp28;
- u_int64_t pim_fpregs_fp29;
- u_int64_t pim_fpregs_fp30;
- u_int64_t pim_fpregs_fp31;
+ uint64_t pim_fpregs_fp0;
+ uint64_t pim_fpregs_fp1;
+ uint64_t pim_fpregs_fp2;
+ uint64_t pim_fpregs_fp3;
+ uint64_t pim_fpregs_fp4;
+ uint64_t pim_fpregs_fp5;
+ uint64_t pim_fpregs_fp6;
+ uint64_t pim_fpregs_fp7;
+ uint64_t pim_fpregs_fp8;
+ uint64_t pim_fpregs_fp9;
+ uint64_t pim_fpregs_fp10;
+ uint64_t pim_fpregs_fp11;
+ uint64_t pim_fpregs_fp12;
+ uint64_t pim_fpregs_fp13;
+ uint64_t pim_fpregs_fp14;
+ uint64_t pim_fpregs_fp15;
+ uint64_t pim_fpregs_fp16;
+ uint64_t pim_fpregs_fp17;
+ uint64_t pim_fpregs_fp18;
+ uint64_t pim_fpregs_fp19;
+ uint64_t pim_fpregs_fp20;
+ uint64_t pim_fpregs_fp21;
+ uint64_t pim_fpregs_fp22;
+ uint64_t pim_fpregs_fp23;
+ uint64_t pim_fpregs_fp24;
+ uint64_t pim_fpregs_fp25;
+ uint64_t pim_fpregs_fp26;
+ uint64_t pim_fpregs_fp27;
+ uint64_t pim_fpregs_fp28;
+ uint64_t pim_fpregs_fp29;
+ uint64_t pim_fpregs_fp30;
+ uint64_t pim_fpregs_fp31;
};
/* The HPMC PIM data. */
@@ -254,7 +254,7 @@
/* The LPMC PIM data. */
struct hp700_pim_lpmc {
- u_int pim_lpmc_hversion_dep[74];
+ uint32_t pim_lpmc_hversion_dep[74];
struct hp700_pim_checks pim_lpmc_checks;
struct hp700_pim_fpregs pim_lpmc_fpregs;
};
@@ -262,122 +262,122 @@
/* The TOC PIM data. */
struct hp700_pim_toc {
struct hp700_pim_regs pim_toc_regs;
- u_int pim_toc_hversion_dep;
- u_int pim_toc_cpu_state;
+ uint32_t pim_toc_hversion_dep;
+ uint32_t pim_toc_cpu_state;
};
struct hp700_pim64_regs {
/* The general registers. */
- u_int64_t pim_regs_r0;
- u_int64_t pim_regs_r1;
- u_int64_t pim_regs_r2;
- u_int64_t pim_regs_r3;
- u_int64_t pim_regs_r4;
- u_int64_t pim_regs_r5;
- u_int64_t pim_regs_r6;
- u_int64_t pim_regs_r7;
- u_int64_t pim_regs_r8;
- u_int64_t pim_regs_r9;
- u_int64_t pim_regs_r10;
- u_int64_t pim_regs_r11;
- u_int64_t pim_regs_r12;
- u_int64_t pim_regs_r13;
- u_int64_t pim_regs_r14;
- u_int64_t pim_regs_r15;
- u_int64_t pim_regs_r16;
- u_int64_t pim_regs_r17;
- u_int64_t pim_regs_r18;
- u_int64_t pim_regs_r19;
- u_int64_t pim_regs_r20;
- u_int64_t pim_regs_r21;
- u_int64_t pim_regs_r22;
- u_int64_t pim_regs_r23;
- u_int64_t pim_regs_r24;
- u_int64_t pim_regs_r25;
- u_int64_t pim_regs_r26;
- u_int64_t pim_regs_r27;
- u_int64_t pim_regs_r28;
- u_int64_t pim_regs_r29;
- u_int64_t pim_regs_r30;
- u_int64_t pim_regs_r31;
+ uint64_t pim_regs_r0;
+ uint64_t pim_regs_r1;
+ uint64_t pim_regs_r2;
+ uint64_t pim_regs_r3;
+ uint64_t pim_regs_r4;
+ uint64_t pim_regs_r5;
+ uint64_t pim_regs_r6;
+ uint64_t pim_regs_r7;
+ uint64_t pim_regs_r8;
+ uint64_t pim_regs_r9;
+ uint64_t pim_regs_r10;
+ uint64_t pim_regs_r11;
+ uint64_t pim_regs_r12;
+ uint64_t pim_regs_r13;
+ uint64_t pim_regs_r14;
+ uint64_t pim_regs_r15;
+ uint64_t pim_regs_r16;
+ uint64_t pim_regs_r17;
+ uint64_t pim_regs_r18;
+ uint64_t pim_regs_r19;
+ uint64_t pim_regs_r20;
+ uint64_t pim_regs_r21;
+ uint64_t pim_regs_r22;
+ uint64_t pim_regs_r23;
+ uint64_t pim_regs_r24;
+ uint64_t pim_regs_r25;
+ uint64_t pim_regs_r26;
+ uint64_t pim_regs_r27;
+ uint64_t pim_regs_r28;
+ uint64_t pim_regs_r29;
+ uint64_t pim_regs_r30;
+ uint64_t pim_regs_r31;
/* The control registers. */
- u_int64_t pim_regs_cr0;
- u_int64_t pim_regs_cr1;
- u_int64_t pim_regs_cr2;
- u_int64_t pim_regs_cr3;
- u_int64_t pim_regs_cr4;
- u_int64_t pim_regs_cr5;
- u_int64_t pim_regs_cr6;
- u_int64_t pim_regs_cr7;
- u_int64_t pim_regs_cr8;
- u_int64_t pim_regs_cr9;
- u_int64_t pim_regs_cr10;
- u_int64_t pim_regs_cr11;
- u_int64_t pim_regs_cr12;
- u_int64_t pim_regs_cr13;
- u_int64_t pim_regs_cr14;
- u_int64_t pim_regs_cr15;
- u_int64_t pim_regs_cr16;
- u_int64_t pim_regs_cr17;
- u_int64_t pim_regs_cr18;
- u_int64_t pim_regs_cr19;
- u_int64_t pim_regs_cr20;
- u_int64_t pim_regs_cr21;
- u_int64_t pim_regs_cr22;
- u_int64_t pim_regs_cr23;
- u_int64_t pim_regs_cr24;
- u_int64_t pim_regs_cr25;
- u_int64_t pim_regs_cr26;
- u_int64_t pim_regs_cr27;
- u_int64_t pim_regs_cr28;
- u_int64_t pim_regs_cr29;
- u_int64_t pim_regs_cr30;
- u_int64_t pim_regs_cr31;
+ uint64_t pim_regs_cr0;
+ uint64_t pim_regs_cr1;
+ uint64_t pim_regs_cr2;
+ uint64_t pim_regs_cr3;
+ uint64_t pim_regs_cr4;
+ uint64_t pim_regs_cr5;
+ uint64_t pim_regs_cr6;
+ uint64_t pim_regs_cr7;
+ uint64_t pim_regs_cr8;
+ uint64_t pim_regs_cr9;
+ uint64_t pim_regs_cr10;
+ uint64_t pim_regs_cr11;
+ uint64_t pim_regs_cr12;
+ uint64_t pim_regs_cr13;
+ uint64_t pim_regs_cr14;
+ uint64_t pim_regs_cr15;
+ uint64_t pim_regs_cr16;
+ uint64_t pim_regs_cr17;
+ uint64_t pim_regs_cr18;
+ uint64_t pim_regs_cr19;
+ uint64_t pim_regs_cr20;
+ uint64_t pim_regs_cr21;
+ uint64_t pim_regs_cr22;
+ uint64_t pim_regs_cr23;
+ uint64_t pim_regs_cr24;
+ uint64_t pim_regs_cr25;
+ uint64_t pim_regs_cr26;
+ uint64_t pim_regs_cr27;
+ uint64_t pim_regs_cr28;
+ uint64_t pim_regs_cr29;
+ uint64_t pim_regs_cr30;
+ uint64_t pim_regs_cr31;
/* The space registers. */
- u_int64_t pim_regs_sr0;
- u_int64_t pim_regs_sr1;
- u_int64_t pim_regs_sr2;
- u_int64_t pim_regs_sr3;
- u_int64_t pim_regs_sr4;
- u_int64_t pim_regs_sr5;
- u_int64_t pim_regs_sr6;
- u_int64_t pim_regs_sr7;
+ uint64_t pim_regs_sr0;
+ uint64_t pim_regs_sr1;
+ uint64_t pim_regs_sr2;
+ uint64_t pim_regs_sr3;
+ uint64_t pim_regs_sr4;
+ uint64_t pim_regs_sr5;
+ uint64_t pim_regs_sr6;
+ uint64_t pim_regs_sr7;
/* The back entries of the instruction address queues. */
- u_int64_t pim_regs_iisq_tail;
- u_int64_t pim_regs_iioq_tail;
+ uint64_t pim_regs_iisq_tail;
+ uint64_t pim_regs_iioq_tail;
};
struct hp700_pim64_checks {
/* The Check Type. */
- u_int pim_check_type;
+ uint32_t pim_check_type;
/*
* The CPU State. In addition to the common PIM_CPU_
* bits defined below, some fields are HPMC-specific.
*/
- u_int pim_check_cpu_state;
+ uint32_t pim_check_cpu_state;
/* The Cache Check word. */
- u_int pim_check_cache;
+ uint32_t pim_check_cache;
/* The TLB Check word. */
- u_int pim_check_tlb;
+ uint32_t pim_check_tlb;
/* The Bus Check word. */
- u_int pim_check_bus;
+ uint32_t pim_check_bus;
/* The Assist Check word. */
- u_int pim_check_assist;
+ uint32_t pim_check_assist;
/* Additional information about the check. */
- u_int pim_check_assist_state;
- u_int pim_check_path_info;
- u_int64_t pim_check_responder;
- u_int64_t pim_check_requestor;
+ uint32_t pim_check_assist_state;
+ uint32_t pim_check_path_info;
+ uint64_t pim_check_responder;
+ uint64_t pim_check_requestor;
};
/* The PARISC 2.0 HPMC PIM data. */
@@ -389,7 +389,7 @@
/* The PARISC 2.0 LPMC PIM data. */
struct hp700_pim64_lpmc {
- u_int64_t pim_lmpc_hversion_dep[74];
+ uint64_t pim_lmpc_hversion_dep[74];
struct hp700_pim64_checks pim_lpmc_checks;
struct hp700_pim_fpregs pim_lpmc_fpregs;
};
@@ -397,6 +397,6 @@
/* The PARISC 2.0 TOC PIM data. */
struct hp700_pim64_toc {
struct hp700_pim64_regs pim_toc_regs;
- u_int pim_toc_hversion_dep;
- u_int pim_toc_cpu_state;
+ uint32_t pim_toc_hversion_dep;
+ uint32_t pim_toc_cpu_state;
};
