Module Name: src Committed By: tsutsui Date: Mon Jul 20 16:25:23 UTC 2009
Modified Files: src/sys/arch/pmax/pmax: dec_3100.c dec_3max.c dec_3maxplus.c dec_3min.c dec_maxine.c Log Message: Sprinkle keyword volatile around device register accesses. To generate a diff of this commit: cvs rdiff -u -r1.47 -r1.48 src/sys/arch/pmax/pmax/dec_3100.c cvs rdiff -u -r1.48 -r1.49 src/sys/arch/pmax/pmax/dec_3max.c cvs rdiff -u -r1.61 -r1.62 src/sys/arch/pmax/pmax/dec_3maxplus.c cvs rdiff -u -r1.63 -r1.64 src/sys/arch/pmax/pmax/dec_3min.c cvs rdiff -u -r1.56 -r1.57 src/sys/arch/pmax/pmax/dec_maxine.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/pmax/pmax/dec_3100.c diff -u src/sys/arch/pmax/pmax/dec_3100.c:1.47 src/sys/arch/pmax/pmax/dec_3100.c:1.48 --- src/sys/arch/pmax/pmax/dec_3100.c:1.47 Mon Mar 16 23:11:14 2009 +++ src/sys/arch/pmax/pmax/dec_3100.c Mon Jul 20 16:25:22 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: dec_3100.c,v 1.47 2009/03/16 23:11:14 dsl Exp $ */ +/* $NetBSD: dec_3100.c,v 1.48 2009/07/20 16:25:22 tsutsui Exp $ */ /* * Copyright (c) 1998 Jonathan Stone. All rights reserved. @@ -105,7 +105,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: dec_3100.c,v 1.47 2009/03/16 23:11:14 dsl Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dec_3100.c,v 1.48 2009/07/20 16:25:22 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -274,11 +274,11 @@ { u_int16_t csr; - csr = *(u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR); + csr = *(volatile u_int16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR); if (csr & KN01_CSR_MERR) { printf("Memory error at 0x%x\n", - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR)); + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR)); panic("Mem error interrupt"); } csr = (csr & ~KN01_CSR_MBZ) | 0xff; Index: src/sys/arch/pmax/pmax/dec_3max.c diff -u src/sys/arch/pmax/pmax/dec_3max.c:1.48 src/sys/arch/pmax/pmax/dec_3max.c:1.49 --- src/sys/arch/pmax/pmax/dec_3max.c:1.48 Mon Mar 16 23:11:14 2009 +++ src/sys/arch/pmax/pmax/dec_3max.c Mon Jul 20 16:25:22 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: dec_3max.c,v 1.48 2009/03/16 23:11:14 dsl Exp $ */ +/* $NetBSD: dec_3max.c,v 1.49 2009/07/20 16:25:22 tsutsui Exp $ */ /* * Copyright (c) 1998 Jonathan Stone. All rights reserved. @@ -106,7 +106,7 @@ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.48 2009/03/16 23:11:14 dsl Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.49 2009/07/20 16:25:22 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -167,7 +167,7 @@ /* no high resolution timer available */ /* clear any memory errors */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; kn02_wbflush(); ipl2spl_table = dec_3max_ipl2spl_table; @@ -179,9 +179,9 @@ * Enable ECC memory correction, turn off LEDs, and * disable all TURBOchannel interrupts. */ - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff); - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; kn02_wbflush(); strcpy(cpu_model, "DECstation 5000/200 (3MAX)"); @@ -197,10 +197,10 @@ * Reset interrupts, clear any errors from newconf probes */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; kn02_wbflush(); - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0; kn02_wbflush(); } @@ -263,9 +263,10 @@ intrtab[(int)cookie].ih_func = handler; intrtab[(int)cookie].ih_arg = arg; - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) & 0x00ffff00; + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) & + 0x00ffff00; csr |= (kn02intrs[i].intrbit << 16); - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; kn02_wbflush(); } @@ -286,7 +287,7 @@ if (ipending & MIPS_INT_MASK_1) { struct clockframe cf; - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); if ((csr & KN02_CSR_PSWARN) && !warned) { warned = 1; printf("WARNING: power supply is overheating!\n"); @@ -310,7 +311,7 @@ _splset(MIPS_SR_INT_IE | (status & MIPS_INT_MASK_1)); if (ipending & MIPS_INT_MASK_0) { - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); csr &= (csr >> KN02_CSR_IOINTEN_SHIFT); if (csr & (KN02_IP_DZ | KN02_IP_LANCE | KN02_IP_SCSI)) { if (csr & KN02_IP_DZ) @@ -349,11 +350,11 @@ u_int32_t erradr, errsyn, csr; /* Fetch error address, ECC chk/syn bits, clear interrupt */ - erradr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR); + erradr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR); errsyn = MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN); - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; kn02_wbflush(); - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); /* Send to kn02/kn03 memory subsystem handler */ dec_mtasic_err(erradr, errsyn, csr & KN02_CSR_BNK32M); Index: src/sys/arch/pmax/pmax/dec_3maxplus.c diff -u src/sys/arch/pmax/pmax/dec_3maxplus.c:1.61 src/sys/arch/pmax/pmax/dec_3maxplus.c:1.62 --- src/sys/arch/pmax/pmax/dec_3maxplus.c:1.61 Mon Mar 16 23:11:14 2009 +++ src/sys/arch/pmax/pmax/dec_3maxplus.c Mon Jul 20 16:25:22 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: dec_3maxplus.c,v 1.61 2009/03/16 23:11:14 dsl Exp $ */ +/* $NetBSD: dec_3maxplus.c,v 1.62 2009/07/20 16:25:22 tsutsui Exp $ */ /* * Copyright (c) 1998 Jonathan Stone. All rights reserved. @@ -106,7 +106,7 @@ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.61 2009/03/16 23:11:14 dsl Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.62 2009/07/20 16:25:22 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -179,7 +179,7 @@ platform.tc_init = dec_3maxplus_tc_init; /* clear any memory errors */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; kn03_wbflush(); ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC); @@ -189,24 +189,24 @@ /* calibrate cpu_mhz value */ mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1); - *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; - *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; + *(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; #if 0 - *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); - *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); - *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); + *(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; #endif /* XXX hard-reset LANCE */ - *(u_int32_t *)(ioasic_base + IOASIC_CSR) |= 0x100; + *(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) |= 0x100; /* sanitize interrupt mask */ kn03_tc3_imask = KN03_INTR_PSWARN; - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask; kn03_wbflush(); - prodtype = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR); + prodtype = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR); prodtype &= KN03_INTR_PROD_JUMPER; /* the bit persists even if INTR register is assigned value 0 */ if (prodtype) @@ -227,10 +227,10 @@ * Reset interrupts, clear any errors from newconf probes */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; kn03_wbflush(); - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; kn03_wbflush(); } @@ -301,7 +301,7 @@ intrtab[(int)cookie].ih_func = handler; intrtab[(int)cookie].ih_arg = arg; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kn03_tc3_imask; kn03_wbflush(); } @@ -362,8 +362,10 @@ do { ifound = 0; - imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); - intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); + imsk = + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK); + intr = + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR); can_serve = intr & imsk; CHECKINTR(SYS_DEV_SCC0, IOASIC_INTR_SCC_0); @@ -405,7 +407,8 @@ xxxintr = can_serve & (ERRORS | PTRLOAD); if (xxxintr) { ifound = 1; - *(u_int32_t *)(ioasic_base + IOASIC_INTR) + *(volatile u_int32_t *) + (ioasic_base + IOASIC_INTR) = intr &~ xxxintr; } } while (ifound); @@ -429,11 +432,11 @@ u_int32_t erradr, errsyn, csr; /* Fetch error address, ECC chk/syn bits, clear interrupt */ - erradr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR); + erradr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR); errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN); - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; kn03_wbflush(); - csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR); + csr = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR); /* Send to kn02/kn03 memory subsystem handler */ dec_mtasic_err(erradr, errsyn, csr & KN03_CSR_BNK32M); @@ -453,7 +456,7 @@ static unsigned dec_3maxplus_get_timecount(struct timecounter *tc) { - return *(u_int32_t*)(ioasic_base + IOASIC_CTR); + return *(volatile u_int32_t *)(ioasic_base + IOASIC_CTR); } static void Index: src/sys/arch/pmax/pmax/dec_3min.c diff -u src/sys/arch/pmax/pmax/dec_3min.c:1.63 src/sys/arch/pmax/pmax/dec_3min.c:1.64 --- src/sys/arch/pmax/pmax/dec_3min.c:1.63 Mon Mar 16 23:11:14 2009 +++ src/sys/arch/pmax/pmax/dec_3min.c Mon Jul 20 16:25:22 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: dec_3min.c,v 1.63 2009/03/16 23:11:14 dsl Exp $ */ +/* $NetBSD: dec_3min.c,v 1.64 2009/07/20 16:25:22 tsutsui Exp $ */ /* * Copyright (c) 1998 Jonathan Stone. All rights reserved. @@ -106,7 +106,7 @@ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.63 2009/03/16 23:11:14 dsl Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.64 2009/07/20 16:25:22 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -176,7 +176,7 @@ platform.tc_init = dec_3min_tc_init; /* clear any memory errors */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; kn02ba_wbflush(); ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); @@ -184,22 +184,22 @@ ipl2spl_table = dec_3min_ipl2spl_table; /* enable posting of MIPS_INT_MASK_3 to CAUSE register */ - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = KMIN_INTR_CLOCK; /* calibrate cpu_mhz value */ mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_3); - *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; - *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; + *(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; #if 0 - *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); - *(u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); - *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6); + *(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00000f00; #endif /* sanitize interrupt mask */ kmin_tc3_imask = (KMIN_INTR_CLOCK|KMIN_INTR_PSWARN|KMIN_INTR_TIMEOUT); - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; /* * The kmin memory hardware seems to wrap memory addresses @@ -228,10 +228,10 @@ * Reset interrupts, clear any errors from newconf probes */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; kn02ba_wbflush(); - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; kn02ba_wbflush(); } @@ -335,7 +335,7 @@ break; } - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = kmin_tc3_imask; kn02ba_wbflush(); } @@ -356,7 +356,7 @@ u_int32_t old_mask; intr_depth++; - old_mask = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); + old_mask = *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK); if (ipending & MIPS_INT_MASK_4) prom_haltbutton(); @@ -367,8 +367,8 @@ u_int32_t intr, imsk, can_serve, turnoff; turnoff = 0; - intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); - imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); + intr = *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR); + imsk = *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK); can_serve = intr & imsk; if (intr & IOASIC_INTR_SCSI_PTR_LOAD) { @@ -385,7 +385,7 @@ turnoff |= IOASIC_INTR_LANCE_READ_E; if (turnoff) - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = ~turnoff; if (intr & KMIN_INTR_TIMEOUT) { kn02ba_errintr(); @@ -407,7 +407,7 @@ /* If clock interrupts were enabled, re-enable them ASAP. */ if (old_mask & KMIN_INTR_CLOCK) { /* ioctl interrupt mask to splclock and higher */ - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask & ~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 | IOASIC_INTR_LANCE|IOASIC_INTR_SCSI); @@ -465,7 +465,7 @@ /* restore entry state */ splhigh(); intr_depth--; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = old_mask; _splset(MIPS_SR_INT_IE | (status & ~cause & MIPS_HARD_INT_MASK)); } Index: src/sys/arch/pmax/pmax/dec_maxine.c diff -u src/sys/arch/pmax/pmax/dec_maxine.c:1.56 src/sys/arch/pmax/pmax/dec_maxine.c:1.57 --- src/sys/arch/pmax/pmax/dec_maxine.c:1.56 Wed Mar 18 10:22:33 2009 +++ src/sys/arch/pmax/pmax/dec_maxine.c Mon Jul 20 16:25:22 2009 @@ -1,4 +1,4 @@ -/* $NetBSD: dec_maxine.c,v 1.56 2009/03/18 10:22:33 cegger Exp $ */ +/* $NetBSD: dec_maxine.c,v 1.57 2009/07/20 16:25:22 tsutsui Exp $ */ /* * Copyright (c) 1998 Jonathan Stone. All rights reserved. @@ -106,7 +106,7 @@ #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.56 2009/03/18 10:22:33 cegger Exp $"); +__KERNEL_RCSID(0, "$NetBSD: dec_maxine.c,v 1.57 2009/07/20 16:25:22 tsutsui Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -174,7 +174,7 @@ /* MAXINE has 1 microsec. free-running high resolution timer */ /* clear any memory errors */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; kn02ca_wbflush(); ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC); @@ -184,19 +184,19 @@ /* calibrate cpu_mhz value */ mc_cpuspeed(ioasic_base+IOASIC_SLOT_8_START, MIPS_INT_MASK_1); - *(u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; - *(u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; + *(volatile u_int32_t *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe; #if 0 - *(u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); - *(u_int32_t *)(ioasic_base + IOASIC_DTOP_DECODE) = 10; - *(u_int32_t *)(ioasic_base + IOASIC_FLOPPY_DECODE) = 13; - *(u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00001fc1; + *(volatile u_int32_t *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4); + *(volatile u_int32_t *)(ioasic_base + IOASIC_DTOP_DECODE) = 10; + *(volatile u_int32_t *)(ioasic_base + IOASIC_FLOPPY_DECODE) = 13; + *(volatile u_int32_t *)(ioasic_base + IOASIC_CSR) = 0x00001fc1; #endif /* sanitize interrupt mask */ xine_tc3_imask = 0; - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask; kn02ca_wbflush(); sprintf(cpu_model, "Personal DECstation 5000/%d (MAXINE)", cpu_mhz); @@ -212,10 +212,10 @@ * Reset interrupts, clear any errors from newconf probes */ - *(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; + *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; kn02ca_wbflush(); - *(u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR) = 0; kn02ca_wbflush(); } @@ -298,7 +298,7 @@ intrtab[(int)cookie].ih_func = handler; intrtab[(int)cookie].ih_arg = arg; - *(u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask; + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK) = xine_tc3_imask; kn02ca_wbflush(); } @@ -340,8 +340,10 @@ do { ifound = 0; - intr = *(u_int32_t *)(ioasic_base + IOASIC_INTR); - imsk = *(u_int32_t *)(ioasic_base + IOASIC_IMSK); + intr = + *(volatile u_int32_t *)(ioasic_base + IOASIC_INTR); + imsk = + *(volatile u_int32_t *)(ioasic_base + IOASIC_IMSK); can_serve = intr & imsk; CHECKINTR(SYS_DEV_DTOP, XINE_INTR_DTOP); @@ -377,7 +379,8 @@ xxxintr = can_serve & (ERRORS | PTRLOAD); if (xxxintr) { ifound = 1; - *(u_int32_t *)(ioasic_base + IOASIC_INTR) + *(volatile u_int32_t *) + (ioasic_base + IOASIC_INTR) = intr &~ xxxintr; } } while (ifound); @@ -401,7 +404,7 @@ static uint32_t dec_maxine_get_timecount(struct timecounter *tc) { - return *(u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR); + return *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR); } static void