Module Name:    src
Committed By:   matt
Date:           Thu Aug  6 16:13:08 UTC 2009

Modified Files:
        src/sys/arch/evbmips/conf: GDIUM std.gdium
        src/sys/arch/mips/conf: files.mips
        src/sys/arch/mips/mips: cache.c

Log Message:
Change MIPS64_LOONGSON2 to MIP3_LOONGSON2 since it's a MIPS3 and not MIPS64.


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbmips/conf/GDIUM \
    src/sys/arch/evbmips/conf/std.gdium
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mips/conf/files.mips
cvs rdiff -u -r1.35 -r1.36 src/sys/arch/mips/mips/cache.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/evbmips/conf/GDIUM
diff -u src/sys/arch/evbmips/conf/GDIUM:1.1 src/sys/arch/evbmips/conf/GDIUM:1.2
--- src/sys/arch/evbmips/conf/GDIUM:1.1	Thu Aug  6 00:50:25 2009
+++ src/sys/arch/evbmips/conf/GDIUM	Thu Aug  6 16:13:07 2009
@@ -1,4 +1,4 @@
-# $NetBSD: GDIUM,v 1.1 2009/08/06 00:50:25 matt Exp $
+# $NetBSD: GDIUM,v 1.2 2009/08/06 16:13:07 matt Exp $
 #
 # GENERIC machine description file
 # 
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GLIB1K-$Revision: 1.1 $"
+#ident 		"GDIUM-$Revision: 1.2 $"
 
 maxusers	16
 
Index: src/sys/arch/evbmips/conf/std.gdium
diff -u src/sys/arch/evbmips/conf/std.gdium:1.1 src/sys/arch/evbmips/conf/std.gdium:1.2
--- src/sys/arch/evbmips/conf/std.gdium:1.1	Thu Aug  6 00:50:25 2009
+++ src/sys/arch/evbmips/conf/std.gdium	Thu Aug  6 16:13:07 2009
@@ -1,4 +1,4 @@
-# $NetBSD: std.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
+# $NetBSD: std.gdium,v 1.2 2009/08/06 16:13:07 matt Exp $
 
 machine evbmips mips
 include		"conf/std"	# MI standard options
@@ -6,7 +6,7 @@
 options 	MIPS3_ENABLE_CLOCK_INTR
 
 # Platform support
-options		MIPS64_LOONGSON2
+options		MIPS3_LOONGSON2
 options		MIPS3
 
 options		EXEC_ELF32	# exec ELF32 binaries

Index: src/sys/arch/mips/conf/files.mips
diff -u src/sys/arch/mips/conf/files.mips:1.60 src/sys/arch/mips/conf/files.mips:1.61
--- src/sys/arch/mips/conf/files.mips:1.60	Sat Aug  1 22:59:52 2009
+++ src/sys/arch/mips/conf/files.mips	Thu Aug  6 16:13:08 2009
@@ -1,9 +1,9 @@
-#	$NetBSD: files.mips,v 1.60 2009/08/01 22:59:52 matt Exp $
+#	$NetBSD: files.mips,v 1.61 2009/08/06 16:13:08 matt Exp $
 #
 
 defflag	opt_cputype.h		NOFPU
 				MIPS64_SB1
-				MIPS64_LOONGSON2F
+				MIPS3_LOONGSON2F
 					# and the rest...
 					# MIPS1	MIPS2 MIPS3 MIPS4 MIPS5
 					# MIPS32 MIPS64

Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.35 src/sys/arch/mips/mips/cache.c:1.36
--- src/sys/arch/mips/mips/cache.c:1.35	Thu Aug  6 15:58:46 2009
+++ src/sys/arch/mips/mips/cache.c	Thu Aug  6 16:13:08 2009
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache.c,v 1.35 2009/08/06 15:58:46 matt Exp $	*/
+/*	$NetBSD: cache.c,v 1.36 2009/08/06 16:13:08 matt Exp $	*/
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.35 2009/08/06 15:58:46 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.36 2009/08/06 16:13:08 matt Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -651,8 +651,7 @@
 		    r10k_pdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
-#endif /* MIPS3 || MIPS4 */
-#ifdef MIPS64_LOONGSON2
+#ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
 		mips_picache_ways = 4;
 		mips_pdcache_ways = 4;
@@ -684,6 +683,7 @@
 		/* Virtually-indexed cache; no use for colors. */
 		break;
 #endif
+#endif /* MIPS3 || MIPS4 */
 	default:
 		panic("can't handle primary cache on impl 0x%x",
 		    MIPS_PRID_IMPL(cpu_id));
@@ -827,8 +827,7 @@
 		    r10k_sdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
-#endif /* MIPS3 || MIPS4 */
-#ifdef MIPS64_LOONGSON2
+#ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
 		mips_sdcache_ways = 4;
 		mips_sdcache_size = 512*1024;
@@ -847,6 +846,7 @@
 		    r4k_sdcache_wb_range_32;
 		break;
 #endif
+#endif /* MIPS3 || MIPS4 */
 
 	default:
 		panic("can't handle secondary cache on impl 0x%x",

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