Module Name: src
Committed By: matt
Date: Tue Aug 11 00:34:29 UTC 2009
Modified Files:
src/sys/arch/mips/include: cache_ls2.h
src/sys/arch/mips/mips: cache.c cache_ls2.c
Log Message:
Flush by increasing way, then increasing addr. flush L1 before L2 (even
though according to the specification it should be needed). Reset
mips_sdcache_size to 0 so we will configure it.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/include/cache_ls2.h
cvs rdiff -u -r1.40 -r1.41 src/sys/arch/mips/mips/cache.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/mips/cache_ls2.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cache_ls2.h
diff -u src/sys/arch/mips/include/cache_ls2.h:1.1 src/sys/arch/mips/include/cache_ls2.h:1.2
--- src/sys/arch/mips/include/cache_ls2.h:1.1 Fri Aug 7 18:39:10 2009
+++ src/sys/arch/mips/include/cache_ls2.h Tue Aug 11 00:34:29 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_ls2.h,v 1.1 2009/08/07 18:39:10 matt Exp $ */
+/* $NetBSD: cache_ls2.h,v 1.2 2009/08/11 00:34:29 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -51,22 +51,22 @@
#define cache_op_ls2_8line_4way(va, op) \
__asm volatile( \
".set noreorder \n\t" \
- "cache %1, 0x00(%0); cache %1, 0x01(%0) \n\t" \
- "cache %1, 0x02(%0); cache %1, 0x03(%0) \n\t" \
- "cache %1, 0x20(%0); cache %1, 0x21(%0) \n\t" \
- "cache %1, 0x22(%0); cache %1, 0x23(%0) \n\t" \
- "cache %1, 0x40(%0); cache %1, 0x41(%0) \n\t" \
- "cache %1, 0x42(%0); cache %1, 0x43(%0) \n\t" \
- "cache %1, 0x60(%0); cache %1, 0x61(%0) \n\t" \
- "cache %1, 0x62(%0); cache %1, 0x63(%0) \n\t" \
- "cache %1, 0x80(%0); cache %1, 0x81(%0) \n\t" \
- "cache %1, 0x82(%0); cache %1, 0x83(%0) \n\t" \
- "cache %1, 0xa0(%0); cache %1, 0xa1(%0) \n\t" \
- "cache %1, 0xa2(%0); cache %1, 0xa3(%0) \n\t" \
- "cache %1, 0xc0(%0); cache %1, 0xc1(%0) \n\t" \
- "cache %1, 0xc2(%0); cache %1, 0xc3(%0) \n\t" \
- "cache %1, 0xe0(%0); cache %1, 0xe1(%0) \n\t" \
- "cache %1, 0xe2(%0); cache %1, 0xe3(%0) \n\t" \
+ "cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
+ "cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \
+ "cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \
+ "cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \
+ "cache %1, 0x01(%0); cache %1, 0x21(%0) \n\t" \
+ "cache %1, 0x41(%0); cache %1, 0x61(%0) \n\t" \
+ "cache %1, 0x81(%0); cache %1, 0xa1(%0) \n\t" \
+ "cache %1, 0xc1(%0); cache %1, 0xe1(%0) \n\t" \
+ "cache %1, 0x02(%0); cache %1, 0x22(%0) \n\t" \
+ "cache %1, 0x42(%0); cache %1, 0x62(%0) \n\t" \
+ "cache %1, 0x82(%0); cache %1, 0xa2(%0) \n\t" \
+ "cache %1, 0xc2(%0); cache %1, 0xe2(%0) \n\t" \
+ "cache %1, 0x03(%0); cache %1, 0x23(%0) \n\t" \
+ "cache %1, 0x43(%0); cache %1, 0x63(%0) \n\t" \
+ "cache %1, 0x83(%0); cache %1, 0xa3(%0) \n\t" \
+ "cache %1, 0xc3(%0); cache %1, 0xe3(%0) \n\t" \
".set reorder" \
: \
: "r" (va), "i" (op) \
Index: src/sys/arch/mips/mips/cache.c
diff -u src/sys/arch/mips/mips/cache.c:1.40 src/sys/arch/mips/mips/cache.c:1.41
--- src/sys/arch/mips/mips/cache.c:1.40 Sun Aug 9 04:05:03 2009
+++ src/sys/arch/mips/mips/cache.c Tue Aug 11 00:34:29 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.40 2009/08/09 04:05:03 matt Exp $ */
+/* $NetBSD: cache.c,v 1.41 2009/08/11 00:34:29 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.40 2009/08/09 04:05:03 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.41 2009/08/11 00:34:29 matt Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -661,6 +661,8 @@
mips3_get_cache_config(csizebase);
+ mips_sdcache_size = 0; /* don't trust config reg */
+
if (mips_picache_size / mips_picache_ways > PAGE_SIZE ||
mips_pdcache_size / mips_pdcache_ways > PAGE_SIZE)
mips_cache_virtual_alias = 1;
Index: src/sys/arch/mips/mips/cache_ls2.c
diff -u src/sys/arch/mips/mips/cache_ls2.c:1.2 src/sys/arch/mips/mips/cache_ls2.c:1.3
--- src/sys/arch/mips/mips/cache_ls2.c:1.2 Fri Aug 7 23:23:58 2009
+++ src/sys/arch/mips/mips/cache_ls2.c Tue Aug 11 00:34:29 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_ls2.c,v 1.2 2009/08/07 23:23:58 matt Exp $ */
+/* $NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.2 2009/08/07 23:23:58 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $");
#include <sys/param.h>
@@ -217,10 +217,12 @@
va = trunc_line(va);
for (; va + 8 * 32 <= eva; va += 8 * 32) {
+ cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);
cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_INV);
}
for (; va < eva; va += 32) {
+ cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV);
cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_INV);
}
@@ -235,10 +237,12 @@
va = trunc_line(va);
for (; va + 8 * 32 <= eva; va += 8 * 32) {
+ cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);
cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_WB_INV);
}
for (; va < eva; va += 32) {
+ cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);
cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_WB_INV);
}
@@ -276,10 +280,12 @@
}
for (; va + 8 * 32 <= eva; va += 8 * 32) {
+ cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
cache_op_ls2_8line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
}
for (; va < eva; va += 32) {
+ cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
cache_op_ls2_line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
}
