Module Name: src
Committed By: matt
Date: Thu Aug 20 23:27:06 UTC 2009
Modified Files:
src/sys/arch/mips/mips [matt-nb5-mips64]: locore.S
Log Message:
Make ABI agnostic (O32 code identical).
To generate a diff of this commit:
cvs rdiff -u -r1.167 -r1.167.38.1 src/sys/arch/mips/mips/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/mips/locore.S
diff -u src/sys/arch/mips/mips/locore.S:1.167 src/sys/arch/mips/mips/locore.S:1.167.38.1
--- src/sys/arch/mips/mips/locore.S:1.167 Wed Oct 17 19:55:38 2007
+++ src/sys/arch/mips/mips/locore.S Thu Aug 20 23:27:06 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.167 2007/10/17 19:55:38 garbled Exp $ */
+/* $NetBSD: locore.S,v 1.167.38.1 2009/08/20 23:27:06 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -84,23 +84,27 @@
/*
* Initialize stack and call machine startup.
*/
- la v1, start
+ PTR_LA v1, start
slt v0, v1, sp
bne v0, zero, 1f
- addu v0, v1, -CALLFRAME_SIZ
- subu v0, v1, sp
+ PTR_ADDU v0, v1, -CALLFRAME_SIZ
+ PTR_SUBU v0, v1, sp
slt v0, v0, 4096 # within 4KB of _start
beq v0, zero, 2f
- addu v0, v1, -CALLFRAME_SIZ
+ PTR_ADDU v0, v1, -CALLFRAME_SIZ
1:
move sp, v0
2:
#ifdef __GP_SUPPORT__
- la gp, _C_LABEL(_gp)
+ PTR_LA gp, _C_LABEL(_gp)
#endif
#ifdef NOFPU /* No FPU; avoid touching FPU registers */
+#ifdef _LP64
+ li t0, MIPS_SR_KX
+#else
li t0, 0 # Disable interrupts and
+#endif
mtc0 t0, MIPS_COP_0_STATUS # the fp coprocessor
COP0_SYNC
#ifdef HPCMIPS_L1CACHE_DISABLE
@@ -113,6 +117,9 @@
#endif /* HPCMIPS_L1CACHE_DISABLE */
#else
mfc0 t0, MIPS_COP_0_STATUS
+#ifdef _LP64
+ or t0, MIPS_SR_KX # turn on XKSEG and XKPHYS
+#endif
or t0, MIPS_SR_COP_1_BIT # Disable interrupts, and
mtc0 t0, MIPS_COP_0_STATUS # enable the fp coprocessor
COP0_HAZARD_FPUENABLE
@@ -129,18 +136,18 @@
#else
cfc1 t1, MIPS_FPU_ID # read FPU ID register
#endif
- sw t0, _C_LABEL(cpu_id) # save PRID register
- sw t1, _C_LABEL(fpu_id) # save FPU ID register
- la MIPS_CURLWP, _C_LABEL(lwp0) # set curlwp, curcpu
- la t0, _C_LABEL(cpu_info_store)
- sw MIPS_CURLWP, CPU_INFO_CURLWP(t0)
- sw t0, L_CPU(MIPS_CURLWP)
+ INT_S t0, _C_LABEL(cpu_id) # save PRID register
+ INT_S t1, _C_LABEL(fpu_id) # save FPU ID register
+ PTR_LA MIPS_CURLWP, _C_LABEL(lwp0) # set curlwp, curcpu
+ PTR_LA t0, _C_LABEL(cpu_info_store)
+ PTR_S MIPS_CURLWP, CPU_INFO_CURLWP(t0)
+ PTR_S t0, L_CPU(MIPS_CURLWP)
jal _C_LABEL(mach_init) # mach_init(a0, a1, a2, a3)
nop
- lw sp, _C_LABEL(proc0paddr) # switch to proc0 stack
+ PTR_L sp, _C_LABEL(proc0paddr) # switch to proc0 stack
nop
- addu sp, sp, USPACE - FRAME_SIZ - CALLFRAME_SIZ
+ PTR_ADDU sp, USPACE - FRAME_SIZ - CALLFRAME_SIZ
jal _C_LABEL(main) # main(void)
nop
PANIC("main() returned") # main never returns
@@ -163,7 +170,7 @@
*/
beq a0, zero, 1f
nop
- lw a2, L_ADDR(a0) # a2 = l->l_addr
+ PTR_L a2, L_ADDR(a0) # a2 = l->l_addr
mfc0 t0, MIPS_COP_0_STATUS
REG_PROLOGUE
REG_S s0, U_PCB_CONTEXT+SF_REG_S0(a2)
@@ -179,51 +186,51 @@
REG_S ra, U_PCB_CONTEXT+SF_REG_RA(a2)
REG_S t0, U_PCB_CONTEXT+SF_REG_SR(a2)
#ifdef IPL_ICU_MASK
- lw t0, _C_LABEL(md_imask)
- sw t0, U_PCB_PPL(a2)
+ INT_L t0, _C_LABEL(md_imask)
+ INT_S t0, U_PCB_PPL(a2)
#endif
REG_EPILOGUE
1:
move s6, a0 # s6 = old lwp
move MIPS_CURLWP, a1 # s7 = new lwp
- subu sp, sp, CALLFRAME_SIZ
- sw ra, CALLFRAME_RA(sp)
+ PTR_SUBU sp, CALLFRAME_SIZ
+ REG_S ra, CALLFRAME_RA(sp)
.mask 0x80000000, -4
/*
* Switch to new context.
*/
- lw t2, _C_LABEL(mips_locoresw) + MIPSX_CPU_SWITCH_RESUME
+ PTR_L t2, _C_LABEL(mips_locoresw) + MIPSX_CPU_SWITCH_RESUME
move a0, MIPS_CURLWP
jal ra, t2
nop
- sw MIPS_CURLWP, CPUVAR(CURLWP)
+ PTR_S MIPS_CURLWP, CPUVAR(CURLWP)
/* Check for restartable atomic sequences (RAS) */
- lw t1, L_PROC(MIPS_CURLWP)
- lw a0, L_ADDR(MIPS_CURLWP)
- lw v1, P_RASLIST(t1)
- addu t0, a0, USPACE - FRAME_SIZ
+ PTR_L t1, L_PROC(MIPS_CURLWP)
+ PTR_L a0, L_ADDR(MIPS_CURLWP)
+ PTR_L v1, P_RASLIST(t1)
+ PTR_ADDU t0, a0, USPACE - FRAME_SIZ
beq v1, zero, 1f
nop
move a0, t1
jal _C_LABEL(ras_lookup)
- lw a1, FRAME_EPC(t0)
- lw a0, L_ADDR(MIPS_CURLWP)
+ PTR_L a1, FRAME_EPC(t0)
+ PTR_L a0, L_ADDR(MIPS_CURLWP)
li v1, -1
beq v1, v0, 1f
- addu t0, a0, USPACE - FRAME_SIZ
- sw v0, FRAME_EPC(t0)
+ PTR_ADDU t0, a0, USPACE - FRAME_SIZ
+ PTR_S v0, FRAME_EPC(t0)
1:
/* New context is now active */
#ifdef IPL_ICU_MASK
# restore ICU state
- lw a0, L_ADDR(MIPS_CURLWP)
- lw t0, U_PCB_PPL(a0)
- sw t0, _C_LABEL(md_imask)
+ PTR_L a0, L_ADDR(MIPS_CURLWP)
+ INT_L t0, U_PCB_PPL(a0)
+ INT_S t0, _C_LABEL(md_imask)
jal _C_LABEL(md_imask_update)
nop
#endif /* IPL_ICU_MASK */
- lw a0, L_ADDR(MIPS_CURLWP)
+ PTR_L a0, L_ADDR(MIPS_CURLWP)
move v0, s6 # Save return value
REG_PROLOGUE
REG_L t0, U_PCB_CONTEXT+SF_REG_SR(a0)
@@ -390,7 +397,13 @@
LEAF(_setsoftintr)
mfc0 v1, MIPS_COP_0_STATUS # save status register
+#if 0
+ li a3, ~MIPS_SR_INT_IE
+ and a3, v1
+ mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#else
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#endif
COP0_SYNC
nop
nop
@@ -407,7 +420,13 @@
LEAF(_clrsoftintr)
mfc0 v1, MIPS_COP_0_STATUS # save status register
+#if 0
+ li a3, ~MIPS_SR_INT_IE
+ and a3, v1
+ mtc0 a3, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#else
mtc0 zero, MIPS_COP_0_STATUS # disable interrupts (2 cycles)
+#endif
COP0_SYNC
nop
nop
@@ -425,7 +444,12 @@
LEAF(_splnone)
mtc0 zero, MIPS_COP_0_CAUSE # clear SOFT_INT bits
COP0_SYNC
+#if 0
+ mfc0 v0, MIPS_COP_0_STATUS # enable all sources
+ ori v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+#else
li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+#endif
DYNAMIC_STATUS_MASK(v0,t0) # machine dependent masking
mtc0 v0, MIPS_COP_0_STATUS # enable all sources
COP0_SYNC
@@ -525,18 +549,18 @@
NESTED(MachFPInterrupt, CALLFRAME_SIZ, ra)
XNESTED(MachFPTrap)
.mask 0x80000000, -4
- subu sp, sp, CALLFRAME_SIZ
- mfc0 t0, MIPS_COP_0_STATUS
- sw ra, CALLFRAME_RA(sp)
- or t0, t0, MIPS_SR_COP_1_BIT
- mtc0 t0, MIPS_COP_0_STATUS
+ PTR_SUBU sp, CALLFRAME_SIZ
+ mfc0 t0, MIPS_COP_0_STATUS
+ REG_S ra, CALLFRAME_RA(sp)
+ or t0, t0, MIPS_SR_COP_1_BIT
+ mtc0 t0, MIPS_COP_0_STATUS
COP0_HAZARD_FPUENABLE
- cfc1 t0, MIPS_FPU_CSR # stall til FP done
- cfc1 t0, MIPS_FPU_CSR # now get status
+ cfc1 t0, MIPS_FPU_CSR # stall til FP done
+ cfc1 t0, MIPS_FPU_CSR # now get status
nop
- sll t2, t0, (31 - 17) # unimplemented operation?
- bgez t2, 3f # no, normal trap
+ sll t2, t0, (31 - 17) # unimplemented operation?
+ bgez t2, 3f # no, normal trap
nop
/*
* We got an unimplemented operation trap so
@@ -547,45 +571,45 @@
*
* fetch the instruction and emulate the instruction.
*/
- bgez a1, 1f # Check the branch delay bit.
+ bgez a1, 1f # Check the branch delay bit.
nop
/*
* The instruction is in the branch delay slot.
*/
- b 2f
- lw a0, 4(a2) # a0 = coproc instruction
+ b 2f
+ lw a0, 4(a2) # a0 = coproc instruction
/*
* This is not in the branch delay slot so calculate the resulting
* PC (epc + 4) into v0 and continue to MachEmulateFP().
*/
1:
- lw a0, 0(a2) # a0 = coproc instruction
+ lw a0, 4(a2) # a0 = coproc instruction
2:
- move a2, a1
+ move a2, a1
/*
* Check to see if the instruction to be emulated is a floating-point
* instruction.
*/
- srl t0, a0, MIPS_OPCODE_SHIFT
- beq t0, MIPS_OPCODE_C1, 4f
+ srl t0, a0, MIPS_OPCODE_SHIFT
+ beq t0, MIPS_OPCODE_C1, 4f
nop
/*
* Send a floating point exception signal to the current LWP.
*/
- li t0, 0xFFFFFF00
- and a1, a1, t0
- ori a1, a1, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
+ li t0, 0xFFFFFF00
+ and a1, a1, t0
+ ori a1, a1, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
REG_PROLOGUE
- REG_S a1, FRAME_CAUSE(a3)
+ REG_S a1, FRAME_CAUSE(a3)
REG_EPILOGUE
- move a1, a0 # code = instruction
- jal _C_LABEL(mips_fpuillinst)
- move a0, MIPS_CURLWP # get current LWP
+ move a1, a0 # code = instruction
+ jal _C_LABEL(mips_fpuillinst)
+ move a0, MIPS_CURLWP # get current LWP
- b FPReturn
+ b FPReturn
nop
/*
@@ -594,133 +618,93 @@
*/
3:
REG_PROLOGUE
- REG_S a1, FRAME_CAUSE(a3)
+ REG_S a1, FRAME_CAUSE(a3)
REG_EPILOGUE
- and a0, t0, ~MIPS_FPU_EXCEPTION_BITS
- ctc1 a0, MIPS_FPU_CSR
+ and a0, t0, ~MIPS_FPU_EXCEPTION_BITS
+ ctc1 a0, MIPS_FPU_CSR
- move a1, t0 # FPU status
- jal _C_LABEL(mips_fpuexcept)
- move a0, MIPS_CURLWP # get current LWP
+ move a1, t0 # FPU status
+ jal _C_LABEL(mips_fpuexcept)
+ move a0, MIPS_CURLWP # get current LWP
- b FPReturn
+ b FPReturn
nop
/*
* Finally, we can call MachEmulateFP() where a0 is the instruction to emulate.
*/
4:
- jal _C_LABEL(MachEmulateFP)
- move a1, a3
+ jal _C_LABEL(MachEmulateFP)
+ move a1, a3
/*
* Turn off the floating point coprocessor and return.
*/
FPReturn:
- mfc0 t0, MIPS_COP_0_STATUS
- lw ra, CALLFRAME_RA(sp)
- and t0, t0, ~MIPS_SR_COP_1_BIT
- mtc0 t0, MIPS_COP_0_STATUS
+ mfc0 t0, MIPS_COP_0_STATUS
+ REG_S ra, CALLFRAME_RA(sp)
+ and t0, t0, ~MIPS_SR_COP_1_BIT
+ mtc0 t0, MIPS_COP_0_STATUS
COP0_SYNC
- j ra
- addu sp, sp, CALLFRAME_SIZ
+ j ra
+ PTR_ADDU sp, CALLFRAME_SIZ
END(MachFPInterrupt)
#endif /* !defined(NOFPU) && !defined(SOFTFLOAT) */
LEAF(mips_pagecopy)
-#if defined(__mips_n32) || defined(_LP64)
.set push
+#if defined(__mips_n32) || defined(_LP64)
.set mips3
- li a2, PAGE_SIZE >> 6
+#endif
+ li a2, PAGE_SIZE / (8 * SZREG)
-1: ld t0, 0(a1)
- ld ta0, 32(a1)
- ld t2, 16(a1)
- ld ta2, 48(a1)
- subu a2, 1
- ld t1, 8(a1)
- ld t3, 24(a1)
- ld ta1, 40(a1)
- ld ta3, 56(a1)
-
- sd t0, 0(a0)
- sd ta0, 32(a0)
- sd t2, 16(a0)
- sd ta2, 48(a0)
- addu a1, 64
- sd t1, 8(a0)
- sd t3, 24(a0)
- sd ta1, 40(a0)
- sd ta3, 56(a0)
- bgtz a2,1b
- addu a0, 64
+1: REG_L t0, (0*SZREG)(a1)
+ REG_L ta0, (4*SZREG)(a1)
+ PTR_SUBU a2, 1
+ REG_L t1, (1*SZREG)(a1)
+ REG_L t2, (2*SZREG)(a1)
+ REG_L t3, (3*SZREG)(a1)
+ REG_L ta1, (5*SZREG)(a1)
+ REG_L ta2, (6*SZREG)(a1)
+ REG_L ta3, (7*SZREG)(a1)
+
+ REG_S t0, (0*SZREG)(a0)
+ REG_S ta0, (4*SZREG)(a0)
+ PTR_ADDU a1, 8*SZREG
+ REG_S t1, (1*SZREG)(a0)
+ REG_S t2, (2*SZREG)(a0)
+ REG_S t3, (3*SZREG)(a0)
+ REG_S ta1, (5*SZREG)(a0)
+ REG_S ta2, (6*SZREG)(a0)
+ REG_S ta3, (7*SZREG)(a0)
+ bgtz a2, 1b
+ PTR_ADDU a0, 8*SZREG
.set pop
-#else
- /* o32 */
- li a2, PAGE_SIZE >> 5
-
-1: lw t0, 0(a1)
- lw ta0, 16(a1)
- subu a2, 1
- lw t1, 4(a1)
- lw t2, 8(a1)
- lw t3, 12(a1)
- lw ta1, 20(a1)
- lw ta2, 24(a1)
- lw ta3, 28(a1)
-
- sw t0, 0(a0)
- sw ta0, 16(a0)
- addu a1, 32
- sw t1, 4(a0)
- sw t2, 8(a0)
- sw t3, 12(a0)
- sw ta1, 20(a0)
- sw ta2, 24(a0)
- sw ta3, 28(a0)
- bgtz a2,1b
- addu a0, 32
-#endif /* __mips_n32 || _LP64 */
j ra
nop
END(mips_pagecopy)
LEAF(mips_pagezero)
/* We can always safely store a 64-bit zero on MIPS3,4,64 */
-#if !defined(MIPS1) && !defined(MIPS32)
.set push
+#if !defined(MIPS1) && !defined(MIPS32)
.set mips3
- li a1, PAGE_SIZE >> 6
+#endif
+ li a1, PAGE_SIZE / (8*SZREG)
-1: sd zero, 0(a0) # try to miss cache first
- sd zero, 32(a0)
- subu a1, 1
- sd zero, 16(a0)
- sd zero, 48(a0)
- sd zero, 8(a0) # fill in cache lines
- sd zero, 40(a0)
- sd zero, 24(a0)
- sd zero, 56(a0)
- bgtz a1,1b
- addu a0, 64
+1: REG_S zero, (0*SZREG)(a0) # try to miss cache first
+ REG_S zero, (4*SZREG)(a0)
+ subu a1, 1
+ REG_S zero, (1*SZREG)(a0) # fill in cache lines
+ REG_S zero, (2*SZREG)(a0)
+ REG_S zero, (3*SZREG)(a0)
+ REG_S zero, (5*SZREG)(a0)
+ REG_S zero, (6*SZREG)(a0)
+ REG_S zero, (7*SZREG)(a0)
+ bgtz a1,1b
+ PTR_ADDU a0, 8*SZREG
.set pop
-#else
- /* o32 */
- li a1, PAGE_SIZE >> 5
-
-1: sw zero, 0(a0)
- sw zero, 16(a0) # try to miss cache first
- subu a1, 1
- sw zero, 4(a0)
- sw zero, 8(a0)
- sw zero, 12(a0)
- sw zero, 20(a0)
- sw zero, 24(a0)
- sw zero, 28(a0)
- bgtz a1,1b
- addu a0, 32
-#endif /* __mips_n32 || _LP64 */
j ra
nop
END(mips_pagezero)
@@ -739,30 +723,50 @@
* stacktrace() -- print a stack backtrace to the console.
* implicitly accesses caller's a0-a3.
*/
-NESTED(stacktrace, CALLFRAME_SIZ+24, ra)
+#if defined(__mips_o32) || defined(__mips_o64)
+#define XCALLFRAME_SIZ (CALLFRAME_SIZ + 6*SZREG)
+#define XCALLFRAME_RA (CALLFRAME_RA + 4*SZREG)
+#endif
+#if defined(__mips_n32) || defined(__mips_n64)
+#define XCALLFRAME_SIZ (CALLFRAME_SIZ + 2*SZREG)
+#define XCALLFRAME_RA (CALLFRAME_RA + 2*SZREG)
+#endif
+NESTED(stacktrace, XCALLFRAME_SIZ, ra)
XNESTED(logstacktrace)
- subu sp, sp, CALLFRAME_SIZ+24 # four arg-passing slots
-
+ PTR_SUBU sp, XCALLFRAME_SIZ # four arg-passing slots
move t0, ra # save caller's PC
- addu t1, sp, CALLFRAME_SIZ+24 # compute caller's SP
+ PTR_ADDU t1, sp, XCALLFRAME_SIZ # save caller's SP
move t2, s8 # non-virtual frame pointer
- la v0, _C_LABEL(printf)
-
- sw ra, 36(sp) # save return address
+ PTR_LA v0, _C_LABEL(printf)
+ REG_S ra, XCALLFRAME_RA(sp) # save return address
+#if defined(__mips_o32) || defined(__mips_o64)
/* a0-a3 are still caller's a0-a3, pass in-place as given. */
- sw t0, 16(sp) # push caller's PC
- sw t1, 20(sp) # push caller's SP
- sw t2, 24(sp) # push caller's FP, in case
- sw zero, 28(sp) # caller's RA on stack
+ REG_S t0, 4*SZREG(sp) # push caller's PC
+ REG_S t1, 5*SZREG(sp) # push caller's SP
+ REG_S t2, 6*SZREG(sp) # push caller's FP, in case
+ REG_S zero, 7*SZREG(sp) # caller's RA on stack
+ /* this uses the slot used for saving s0 in the callframe */
jal _C_LABEL(stacktrace_subr)
- sw v0, 32(sp) # push printf
+ REG_S v0, 8*SZREG(sp) # push printf
+#endif
+#if defined(__mips_n32) || defined(__mips_n64)
+ move a4, t0 # pass caller's PC
+ move a5, t1 # pass caller's SP
+ move a6, t2 # pass caller's FP, in case
+ move a7, zero # caller's RA on stack
+ /* this uses the slot used for saving s0 in the callframe */
+ jal _C_LABEL(stacktrace_subr)
+ REG_S v0, 0(sp) # push printf
+#endif
- lw ra, 36(sp)
- addu sp, sp, CALLFRAME_SIZ+24
+ REG_L ra, XCALLFRAME_RA(sp)
+ PTR_ADDU sp, XCALLFRAME_SIZ
j ra
nop
+#undef XCALLFRAME_RA
+#undef XCALLFRAME_SIZ
END(stacktrace)
#endif /* DEBUG || DDB */
#endif /* DDB_TRACE */
