Module Name: src
Committed By: matt
Date: Sun Aug 30 10:01:04 UTC 2009
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpuregs.h locore.h
Log Message:
Add RMI company id.
Add some RMI processor ids.
Add CP0 EBASE defintion.
To generate a diff of this commit:
cvs rdiff -u -r1.74.28.2 -r1.74.28.3 src/sys/arch/mips/include/cpuregs.h
cvs rdiff -u -r1.78.36.1.2.2 -r1.78.36.1.2.3 \
src/sys/arch/mips/include/locore.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.74.28.2 src/sys/arch/mips/include/cpuregs.h:1.74.28.3
--- src/sys/arch/mips/include/cpuregs.h:1.74.28.2 Fri Aug 21 17:26:23 2009
+++ src/sys/arch/mips/include/cpuregs.h Sun Aug 30 10:01:03 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.74.28.2 2009/08/21 17:26:23 matt Exp $ */
+/* $NetBSD: cpuregs.h,v 1.74.28.3 2009/08/30 10:01:03 matt Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -451,6 +451,7 @@
* 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
* 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
* 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
+ * 15/1 MIPS_COP_0_EBASE 3333 Exception Base
* 16 MIPS_COP_0_CONFIG 3333 Configuration register.
* 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
* 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
@@ -806,6 +807,27 @@
#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
/*
+ * CPU processor revision IDs for company ID == 12 (RMI)
+ */
+#define MIPS_XLR732 0x00 /* RMI XLS732-C ISA 64 */
+#define MIPS_XLR716 0x02 /* RMI XLS716-C ISA 64 */
+#define MIPS_XLR532 0x08 /* RMI XLS532-C ISA 64 */
+#define MIPS_XLR516 0x0a /* RMI XLS516-C ISA 64 */
+#define MIPS_XLR508 0x0b /* RMI XLS508-C ISA 64 */
+#define MIPS_XLR308 0x0f /* RMI XLS308-C ISA 64 */
+#define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
+#define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
+#define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
+#define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
+#define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
+#define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
+#define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
+#define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
+#define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
+#define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
+#define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
+
+/*
* FPU processor revision ID
*/
#define MIPS_SOFT 0x00 /* Software emulation ISA I */
Index: src/sys/arch/mips/include/locore.h
diff -u src/sys/arch/mips/include/locore.h:1.78.36.1.2.2 src/sys/arch/mips/include/locore.h:1.78.36.1.2.3
--- src/sys/arch/mips/include/locore.h:1.78.36.1.2.2 Fri Aug 21 17:32:00 2009
+++ src/sys/arch/mips/include/locore.h Sun Aug 30 10:01:03 2009
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.78.36.1.2.2 2009/08/21 17:32:00 matt Exp $ */
+/* $NetBSD: locore.h,v 1.78.36.1.2.3 2009/08/30 10:01:03 matt Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -399,6 +399,7 @@
/* 0x09 unannounced */
/* 0x0a unannounced */
#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
+#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */
#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
#ifdef _KERNEL
