Module Name: src
Committed By: matt
Date: Mon Nov 9 17:51:53 UTC 2009
Modified Files:
src/gnu/dist/binutils/opcodes [matt-nb5-mips64]: mips-opc.c
Log Message:
Fix missing bits
To generate a diff of this commit:
cvs rdiff -u -r1.1.1.3.32.1 -r1.1.1.3.32.2 \
src/gnu/dist/binutils/opcodes/mips-opc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/gnu/dist/binutils/opcodes/mips-opc.c
diff -u src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.1 src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.2
--- src/gnu/dist/binutils/opcodes/mips-opc.c:1.1.1.3.32.1 Mon Nov 9 17:38:20 2009
+++ src/gnu/dist/binutils/opcodes/mips-opc.c Mon Nov 9 17:51:53 2009
@@ -802,8 +802,8 @@
/* mthc2 is at the bottom of the table. */
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
-{"mfcr", "t,s", 0x70000018, 0xfc00003f, WR_t|RD_s, 0, I64 },
-{"mtcr", "t,s", 0x70000019, 0xfc00003f, WR_t|RD_s, 0, I64 },
+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_t|RD_s, 0, I64 },
+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, WR_t|RD_s, 0, I64 },
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
