Module Name: src
Committed By: msaitoh
Date: Mon Aug 20 08:53:48 UTC 2018
Modified Files:
src/sys/arch/x86/include: specialreg.h
src/sys/arch/x86/x86: procfs_machdep.c
Log Message:
OK'd by maxv:
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
To generate a diff of this commit:
cvs rdiff -u -r1.129 -r1.130 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/x86/x86/procfs_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.129 src/sys/arch/x86/include/specialreg.h:1.130
--- src/sys/arch/x86/include/specialreg.h:1.129 Tue Aug 7 10:50:12 2018
+++ src/sys/arch/x86/include/specialreg.h Mon Aug 20 08:53:48 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.129 2018/08/07 10:50:12 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.130 2018/08/20 08:53:48 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -402,13 +402,14 @@
#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
+#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
#define CPUID_SEF_FLAGS2 "\20" \
"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
"\33" "IBRS" "\34" "STIBP" \
- "\36" "ARCH_CAP" "\40" "SSBD"
+ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD"
/*
* CPUID Processor extended state Enumeration Fn0000000d
@@ -661,7 +662,10 @@
#define IA32_ARCH_RDCL_NO 0x01
#define IA32_ARCH_IBRS_ALL 0x02
#define IA32_ARCH_RSBA 0x04
+#define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
#define IA32_ARCH_SSB_NO 0x10
+#define MSR_IA32_FLUSH_CMD 0x10b
+#define IA32_FLUSH_CMD_L1D_FLUSH 0x01
#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
Index: src/sys/arch/x86/x86/procfs_machdep.c
diff -u src/sys/arch/x86/x86/procfs_machdep.c:1.23 src/sys/arch/x86/x86/procfs_machdep.c:1.24
--- src/sys/arch/x86/x86/procfs_machdep.c:1.23 Wed May 23 05:04:39 2018
+++ src/sys/arch/x86/x86/procfs_machdep.c Mon Aug 20 08:53:48 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: procfs_machdep.c,v 1.23 2018/05/23 05:04:39 msaitoh Exp $ */
+/* $NetBSD: procfs_machdep.c,v 1.24 2018/08/20 08:53:48 msaitoh Exp $ */
/*
* Copyright (c) 2001 Wasabi Systems, Inc.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.23 2018/05/23 05:04:39 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.24 2018/08/20 08:53:48 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -190,7 +190,8 @@ static const char * const x86_features[]
NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, "arch_capabilities", NULL, "ssbd"},
+ NULL, NULL, NULL, NULL,
+ "flush_l1d", "arch_capabilities", NULL, "ssbd"},
};
static int procfs_getonecpu(int, struct cpu_info *, char *, size_t *);
