Module Name: src
Committed By: mrg
Date: Thu Sep 13 08:25:55 UTC 2018
Modified Files:
src/sys/external/bsd/drm2/dist/drm/i915: i915_dma.c i915_drv.c
i915_drv.h i915_gem_stolen.c i915_irq.c i915_reg.h intel_csr.c
intel_ddi.c intel_display.c intel_dp.c intel_fbc.c
intel_guc_loader.c intel_i2c.c intel_mocs.c intel_panel.c
intel_pm.c intel_ringbuffer.c intel_runtime_pm.c
src/sys/external/bsd/drm2/dist/include/drm: i915_pciids.h
Log Message:
add support for kabylake and skylake GT4 (untested) GPUs.
largely taken from openbsd and linux 4.13 trees (which
have this code identical), with mimimal porting to netbsd.
i have not installed (and thus tested) the newer referenced
firmware files.
only real local change is to fix IS_BROXTON() macro to check
the things valid in this era of drm. previous match would
attach on KBL, and then a loop would never exit.
tested on kabylake P630. needs mesa 11.x or newer for GL
to work.
ok @riastradh.
To generate a diff of this commit:
cvs rdiff -u -r1.25 -r1.26 src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c
cvs rdiff -u -r1.15 -r1.16 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c \
src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c
cvs rdiff -u -r1.27 -r1.28 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h
cvs rdiff -u -r1.10 -r1.11 \
src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c \
src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c
cvs rdiff -u -r1.16 -r1.17 src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c \
src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c
cvs rdiff -u -r1.4 -r1.5 src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h \
src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c
cvs rdiff -u -r1.7 -r1.8 src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c
cvs rdiff -u -r1.22 -r1.23 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c
cvs rdiff -u -r1.18 -r1.19 src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c
cvs rdiff -u -r1.3 -r1.4 src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c
cvs rdiff -u -r1.12 -r1.13 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c
cvs rdiff -u -r1.2 -r1.3 src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c
cvs rdiff -u -r1.8 -r1.9 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c
cvs rdiff -u -r1.5 -r1.6 \
src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c
cvs rdiff -u -r1.2 -r1.3 \
src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c:1.25 src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c:1.26
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c:1.25 Tue Aug 28 03:41:38 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_dma.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_dma.c,v 1.25 2018/08/28 03:41:38 riastradh Exp $ */
+/* $NetBSD: i915_dma.c,v 1.26 2018/09/13 08:25:55 mrg Exp $ */
/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
*/
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_dma.c,v 1.25 2018/08/28 03:41:38 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_dma.c,v 1.26 2018/09/13 08:25:55 mrg Exp $");
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -693,7 +693,8 @@ static void gen9_sseu_info_init(struct d
* supports EU power gating on devices with more than one EU
* pair per subslice.
*/
- info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
+ info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+ (info->slice_total > 1));
info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
info->has_eu_pg = (info->eu_per_subslice > 2);
}
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c:1.15 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c:1.16
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c:1.15 Mon Aug 27 15:22:54 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_drv.c,v 1.15 2018/08/27 15:22:54 riastradh Exp $ */
+/* $NetBSD: i915_drv.c,v 1.16 2018/09/13 08:25:55 mrg Exp $ */
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
*/
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_drv.c,v 1.15 2018/08/27 15:22:54 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_drv.c,v 1.16 2018/09/13 08:25:55 mrg Exp $");
#include <linux/device.h>
#include <linux/acpi.h>
@@ -406,6 +406,34 @@ static const struct intel_device_info in
IVB_CURSOR_OFFSETS,
};
+static const struct intel_device_info intel_kabylake_info = {
+ .is_kabylake = 1,
+ .gen = 9,
+ .num_pipes = 3,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
+ .has_llc = 1,
+ .has_ddi = 1,
+ .has_fpga_dbg = 1,
+ .has_fbc = 1,
+ GEN_DEFAULT_PIPEOFFSETS,
+ IVB_CURSOR_OFFSETS,
+};
+
+static const struct intel_device_info intel_kabylake_gt3_info = {
+ .is_kabylake = 1,
+ .gen = 9,
+ .num_pipes = 3,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+ .has_llc = 1,
+ .has_ddi = 1,
+ .has_fpga_dbg = 1,
+ .has_fbc = 1,
+ GEN_DEFAULT_PIPEOFFSETS,
+ IVB_CURSOR_OFFSETS,
+};
+
/*
* Make sure any device matches here are from most specific to most
* general. For example, since the Quanta match is based on the subsystem
@@ -446,7 +474,13 @@ static const struct intel_device_info in
INTEL_SKL_GT1_IDS(&intel_skylake_info), \
INTEL_SKL_GT2_IDS(&intel_skylake_info), \
INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
- INTEL_BXT_IDS(&intel_broxton_info)
+ INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), \
+ INTEL_BXT_IDS(&intel_broxton_info), \
+ INTEL_KBL_GT1_IDS(&intel_kabylake_info), \
+ INTEL_KBL_GT2_IDS(&intel_kabylake_info), \
+ INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), \
+ INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info)
+
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_PCI_IDS,
@@ -475,7 +509,7 @@ static enum intel_pch intel_virt_detect_
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ret = PCH_LPT;
DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
- } else if (IS_SKYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
}
@@ -544,11 +578,17 @@ void intel_detect_pch(struct drm_device
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
- WARN_ON(!IS_SKYLAKE(dev));
+ WARN_ON(!IS_SKYLAKE(dev) &&
+ !IS_KABYLAKE(dev));
} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
- WARN_ON(!IS_SKYLAKE(dev));
+ WARN_ON(!IS_SKYLAKE(dev) &&
+ !IS_KABYLAKE(dev));
+ } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_KBP;
+ DRM_DEBUG_KMS("Found KabyPoint PCH\n");
+ WARN_ON(!IS_KABYLAKE(dev_priv));
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
pch->subsystem_vendor == 0x1af4 &&
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.15 src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.16
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c:1.15 Mon Aug 27 15:09:35 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_pm.c,v 1.15 2018/08/27 15:09:35 riastradh Exp $ */
+/* $NetBSD: intel_pm.c,v 1.16 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2012 Intel Corporation
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.15 2018/08/27 15:09:35 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_pm.c,v 1.16 2018/09/13 08:25:55 mrg Exp $");
#include <linux/bitops.h>
#include <linux/cpufreq.h>
@@ -4727,7 +4727,8 @@ static void gen6_init_rps_frequencies(st
dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+ IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
ret = sandybridge_pcode_read(dev_priv,
HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status);
@@ -4739,7 +4740,7 @@ static void gen6_init_rps_frequencies(st
dev_priv->rps.max_freq);
}
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
/* Store the frequency values in 16.66 MHZ units, which is
the natural hardware unit for SKL */
dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
@@ -5102,7 +5103,7 @@ static void __gen6_update_ring_freq(stru
/* convert DDR frequency from units of 266.6MHz to bandwidth */
min_ring_freq = mult_frac(min_ring_freq, 8, 3);
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
@@ -5120,7 +5121,7 @@ static void __gen6_update_ring_freq(stru
int diff = max_gpu_freq - gpu_freq;
unsigned int ia_freq = 0, ring_freq = 0;
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
/*
* ring_freq = 2 * GT. ring_freq is in 100MHz units
* No floor required for ring frequency on SKL.
@@ -6250,7 +6251,7 @@ static void intel_gen6_powersave_work(st
} else if (INTEL_INFO(dev)->gen >= 9) {
gen9_enable_rc6(dev);
gen9_enable_rps(dev);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
__gen6_update_ring_freq(dev);
} else if (IS_BROADWELL(dev)) {
gen8_enable_rps(dev);
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.27 src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.28
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h:1.27 Mon Aug 27 15:22:54 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_drv.h,v 1.27 2018/08/27 15:22:54 riastradh Exp $ */
+/* $NetBSD: i915_drv.h,v 1.28 2018/09/13 08:25:55 mrg Exp $ */
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
@@ -800,6 +800,7 @@ struct intel_csr {
func(is_valleyview) sep \
func(is_haswell) sep \
func(is_skylake) sep \
+ func(is_kabylake) sep \
func(is_preliminary) sep \
func(has_fbc) sep \
func(has_pipe_cxsr) sep \
@@ -1027,6 +1028,7 @@ enum intel_pch {
PCH_CPT, /* Cougarpoint PCH */
PCH_LPT, /* Lynxpoint PCH */
PCH_SPT, /* Sunrisepoint PCH */
+ PCH_KBP, /* Kabypoint PCH */
PCH_NOP,
};
@@ -2521,6 +2523,16 @@ struct drm_i915_cmd_table {
#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
+#define REVID_FOREVER (0xff)
+
+/*
+ * Return true if revision is in range [since,until] inclusive.
+ *
+ * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
+ */
+#define IS_REVID(p, since, until) \
+ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
+
#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
@@ -2544,10 +2556,12 @@ struct drm_i915_cmd_table {
INTEL_DEVID(dev) == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
-#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
-#define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
+#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
+#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
+#define IS_BROXTON(dev) (!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev) && \
+ IS_GEN9(dev))
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
(INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
@@ -2575,6 +2589,14 @@ struct drm_i915_cmd_table {
#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
INTEL_DEVID(dev) == 0x1915 || \
INTEL_DEVID(dev) == 0x191E)
+#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
+ INTEL_DEVID(dev) == 0x5913 || \
+ INTEL_DEVID(dev) == 0x5916 || \
+ INTEL_DEVID(dev) == 0x5921 || \
+ INTEL_DEVID(dev) == 0x5926)
+#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
+ INTEL_DEVID(dev) == 0x5915 || \
+ INTEL_DEVID(dev) == 0x591E)
#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
(INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
@@ -2589,10 +2611,23 @@ struct drm_i915_cmd_table {
#define SKL_REVID_E0 (0x4)
#define SKL_REVID_F0 (0x5)
+#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+
#define BXT_REVID_A0 (0x0)
+#define BXT_REVID_A1 (0x1)
#define BXT_REVID_B0 (0x3)
#define BXT_REVID_C0 (0x9)
+#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+
+#define KBL_REVID_A0 (0x0)
+#define KBL_REVID_B0 (0x1)
+#define KBL_REVID_C0 (0x2)
+#define KBL_REVID_D0 (0x3)
+#define KBL_REVID_E0 (0x4)
+
+#define IS_KBL_REVID(p, since, until) (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
@@ -2689,10 +2724,12 @@ struct drm_i915_cmd_table {
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
+#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
+#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c:1.10 src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c:1.11
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c:1.10 Mon Aug 27 07:20:39 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_stolen.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_gem_stolen.c,v 1.10 2018/08/27 07:20:39 riastradh Exp $ */
+/* $NetBSD: i915_gem_stolen.c,v 1.11 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2008-2012 Intel Corporation
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_gem_stolen.c,v 1.10 2018/08/27 07:20:39 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_gem_stolen.c,v 1.11 2018/09/13 08:25:55 mrg Exp $");
#include <linux/printk.h>
#include <linux/err.h>
@@ -465,7 +465,8 @@ int i915_gem_init_stolen(struct drm_devi
&reserved_size);
break;
default:
- if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+ if (IS_BROADWELL(dev_priv) ||
+ IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
bdw_get_stolen_reserved(dev_priv, &reserved_base,
&reserved_size);
else
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c:1.10 src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c:1.11
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c:1.10 Mon Aug 27 07:27:16 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_panel.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_panel.c,v 1.10 2018/08/27 07:27:16 riastradh Exp $ */
+/* $NetBSD: intel_panel.c,v 1.11 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2006-2010 Intel Corporation
@@ -31,7 +31,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_panel.c,v 1.10 2018/08/27 07:27:16 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_panel.c,v 1.11 2018/09/13 08:25:55 mrg Exp $");
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -1782,7 +1782,8 @@ intel_panel_init_backlight_funcs(struct
panel->backlight.disable = bxt_disable_backlight;
panel->backlight.set = bxt_set_backlight;
panel->backlight.get = bxt_get_backlight;
- } else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev)) {
+ } else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev) ||
+ HAS_PCH_KBP(dev)) {
panel->backlight.setup = lpt_setup_backlight;
panel->backlight.enable = lpt_enable_backlight;
panel->backlight.disable = lpt_disable_backlight;
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.16 src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.17
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c:1.16 Mon Aug 27 14:52:56 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_irq.c,v 1.16 2018/08/27 14:52:56 riastradh Exp $ */
+/* $NetBSD: i915_irq.c,v 1.17 2018/09/13 08:25:55 mrg Exp $ */
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
*/
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.16 2018/08/27 14:52:56 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_irq.c,v 1.17 2018/09/13 08:25:55 mrg Exp $");
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -2381,7 +2381,7 @@ static irqreturn_t gen8_irq_handler(DRM_
I915_WRITE(SDEIIR, pch_iir);
ret = IRQ_HANDLED;
- if (HAS_PCH_SPT(dev_priv))
+ if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
spt_irq_handler(dev, pch_iir);
else
cpt_irq_handler(dev, pch_iir);
@@ -4572,7 +4572,7 @@ void intel_irq_init(struct drm_i915_priv
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_BROXTON(dev))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (HAS_PCH_SPT(dev))
+ else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c:1.16 src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c:1.17
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c:1.16 Mon Aug 27 06:16:37 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_i2c.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_i2c.c,v 1.16 2018/08/27 06:16:37 riastradh Exp $ */
+/* $NetBSD: intel_i2c.c,v 1.17 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright (c) 2006 Dave Airlie <airl...@linux.ie>
@@ -29,7 +29,7 @@
* Chris Wilson <ch...@chris-wilson.co.uk>
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_i2c.c,v 1.16 2018/08/27 06:16:37 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_i2c.c,v 1.17 2018/09/13 08:25:55 mrg Exp $");
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
@@ -80,7 +80,7 @@ static const struct gmbus_pin *get_gmbus
{
if (IS_BROXTON(dev_priv))
return &gmbus_pins_bxt[pin];
- else if (IS_SKYLAKE(dev_priv))
+ else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return &gmbus_pins_skl[pin];
else if (IS_BROADWELL(dev_priv))
return &gmbus_pins_bdw[pin];
@@ -95,7 +95,7 @@ bool intel_gmbus_is_valid_pin(struct drm
if (IS_BROXTON(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt);
- else if (IS_SKYLAKE(dev_priv))
+ else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl);
else if (IS_BROADWELL(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bdw);
Index: src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h
diff -u src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.4 src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.5
--- src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h:1.4 Mon Aug 27 07:06:25 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/i915_reg.h Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_reg.h,v 1.4 2018/08/27 07:06:25 riastradh Exp $ */
+/* $NetBSD: i915_reg.h,v 1.5 2018/09/13 08:25:55 mrg Exp $ */
/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
@@ -1590,6 +1590,12 @@ enum skl_disp_power_wells {
#define GEN7_TLB_RD_ADDR 0x4700
+#define GAMT_CHKN_BIT_REG 0x4ab8
+#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
+
+#define GEN9_GAMT_ECO_REG_RW_IA 0x4ab0
+#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
+
#if 0
#define PRB0_TAIL 0x02030
#define PRB0_HEAD 0x02034
@@ -5921,6 +5927,9 @@ enum skl_disp_power_wells {
#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
+#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
+#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
+#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
#define FF_SLICE_CS_CHICKEN2 0x20e4
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
@@ -5930,6 +5939,7 @@ enum skl_disp_power_wells {
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 0x7014
+# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
#define HIZ_CHICKEN 0x7018
@@ -6766,6 +6776,7 @@ enum skl_disp_power_wells {
#define GEN7_UCGCTL4 0x940c
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
+#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
#define GEN6_RCGCTL1 0x9410
#define GEN6_RCGCTL2 0x9414
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c:1.4 src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c:1.5
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c:1.4 Mon Aug 27 15:09:35 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_csr.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_csr.c,v 1.4 2018/08/27 15:09:35 riastradh Exp $ */
+/* $NetBSD: intel_csr.c,v 1.5 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2014 Intel Corporation
@@ -24,7 +24,7 @@
*
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_csr.c,v 1.4 2018/08/27 15:09:35 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_csr.c,v 1.5 2018/09/13 08:25:55 mrg Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -48,9 +48,11 @@ __KERNEL_RCSID(0, "$NetBSD: intel_csr.c,
* be moved to FW_FAILED.
*/
+#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
+MODULE_FIRMWARE(I915_CSR_KBL);
MODULE_FIRMWARE(I915_CSR_SKL);
MODULE_FIRMWARE(I915_CSR_BXT);
@@ -184,6 +186,14 @@ struct stepping_info {
char substepping;
};
+/*
+ * Kabylake derivated from Skylake H0, so SKL H0
+ * is the right firmware for KBL A0 (revid 0).
+ */
+static const struct stepping_info kbl_stepping_info[] = {
+ {'H', '0'}, {'I', '0'}
+};
+
static const struct stepping_info skl_stepping_info[] = {
{'A', '0'}, {'B', '0'}, {'C', '0'},
{'D', '0'}, {'E', '0'}, {'F', '0'},
@@ -198,7 +208,10 @@ static struct stepping_info bxt_stepping
static char intel_get_stepping(struct drm_device *dev)
{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ if (IS_KABYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(kbl_stepping_info)))
+ return kbl_stepping_info[dev->pdev->revision].stepping;
+ else if (IS_SKYLAKE(dev) && (dev->pdev->revision <
ARRAY_SIZE(skl_stepping_info)))
return skl_stepping_info[dev->pdev->revision].stepping;
else if (IS_BROXTON(dev) && (dev->pdev->revision <
@@ -210,7 +223,10 @@ static char intel_get_stepping(struct dr
static char intel_get_substepping(struct drm_device *dev)
{
- if (IS_SKYLAKE(dev) && (dev->pdev->revision <
+ if (IS_KABYLAKE(dev) && (dev->pdev->revision <
+ ARRAY_SIZE(kbl_stepping_info)))
+ return kbl_stepping_info[dev->pdev->revision].substepping;
+ else if (IS_SKYLAKE(dev) && (dev->pdev->revision <
ARRAY_SIZE(skl_stepping_info)))
return skl_stepping_info[dev->pdev->revision].substepping;
else if (IS_BROXTON(dev) && (dev->pdev->revision <
@@ -436,7 +452,9 @@ void intel_csr_ucode_init(struct drm_dev
if (!HAS_CSR(dev))
return;
- if (IS_SKYLAKE(dev))
+ if (IS_KABYLAKE(dev))
+ csr->fw_path = I915_CSR_KBL;
+ else if (IS_SKYLAKE(dev))
csr->fw_path = I915_CSR_SKL;
else if (IS_BROXTON(dev_priv))
csr->fw_path = I915_CSR_BXT;
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c:1.7 src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c:1.8
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c:1.7 Mon Aug 27 07:26:08 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_ddi.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_ddi.c,v 1.7 2018/08/27 07:26:08 riastradh Exp $ */
+/* $NetBSD: intel_ddi.c,v 1.8 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2012 Intel Corporation
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_ddi.c,v 1.7 2018/08/27 07:26:08 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_ddi.c,v 1.8 2018/09/13 08:25:55 mrg Exp $");
#include <linux/math64.h>
@@ -360,10 +360,10 @@ static const struct ddi_buf_trans *skl_g
{
const struct ddi_buf_trans *ddi_translations;
- if (IS_SKL_ULX(dev)) {
+ if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
ddi_translations = skl_y_ddi_translations_dp;
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
- } else if (IS_SKL_ULT(dev)) {
+ } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
ddi_translations = skl_u_ddi_translations_dp;
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
} else {
@@ -380,7 +380,7 @@ static const struct ddi_buf_trans *skl_g
struct drm_i915_private *dev_priv = dev->dev_private;
const struct ddi_buf_trans *ddi_translations;
- if (IS_SKL_ULX(dev)) {
+ if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
if (dev_priv->edp_low_vswing) {
ddi_translations = skl_y_ddi_translations_edp;
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
@@ -388,7 +388,7 @@ static const struct ddi_buf_trans *skl_g
ddi_translations = skl_y_ddi_translations_dp;
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
}
- } else if (IS_SKL_ULT(dev)) {
+ } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
if (dev_priv->edp_low_vswing) {
ddi_translations = skl_u_ddi_translations_edp;
*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
@@ -415,7 +415,7 @@ skl_get_buf_trans_hdmi(struct drm_device
{
const struct ddi_buf_trans *ddi_translations;
- if (IS_SKL_ULX(dev)) {
+ if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
ddi_translations = skl_y_ddi_translations_hdmi;
*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
} else {
@@ -455,7 +455,7 @@ static void intel_prepare_ddi_buffers(st
bxt_ddi_vswing_sequence(dev, hdmi_level, port,
INTEL_OUTPUT_HDMI);
return;
- } else if (IS_SKYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
ddi_translations_fdi = NULL;
ddi_translations_dp =
skl_get_buf_trans_dp(dev, &n_dp_entries);
@@ -1199,7 +1199,7 @@ void intel_ddi_clock_get(struct intel_en
if (INTEL_INFO(dev)->gen <= 8)
hsw_ddi_clock_get(encoder, pipe_config);
- else if (IS_SKYLAKE(dev))
+ else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
skl_ddi_clock_get(encoder, pipe_config);
else if (IS_BROXTON(dev))
bxt_ddi_clock_get(encoder, pipe_config);
@@ -1796,7 +1796,7 @@ bool intel_ddi_pll_select(struct intel_c
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_new_encoder(crtc_state);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
return skl_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
else if (IS_BROXTON(dev))
@@ -2279,7 +2279,7 @@ uint32_t ddi_signal_levels(struct intel_
level = translate_signal_level(signal_levels);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
skl_ddi_set_iboost(dev, level, port, encoder->type);
else if (IS_BROXTON(dev))
bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
@@ -2302,7 +2302,7 @@ static void intel_ddi_pre_enable(struct
intel_edp_panel_on(intel_dp);
}
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
uint32_t dpll = crtc->config->ddi_pll_sel;
uint32_t val;
@@ -2397,7 +2397,7 @@ static void intel_ddi_post_disable(struc
intel_edp_panel_off(intel_dp);
}
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port)));
else if (INTEL_INFO(dev)->gen < 9)
@@ -3008,14 +3008,14 @@ void intel_ddi_pll_init(struct drm_devic
struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t val = I915_READ(LCPLL_CTL);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
skl_shared_dplls_init(dev_priv);
else if (IS_BROXTON(dev))
bxt_shared_dplls_init(dev_priv);
else
hsw_shared_dplls_init(dev_priv);
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
int cdclk_freq;
cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c:1.22 src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c:1.23
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c:1.22 Sun Sep 2 17:36:57 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_display.c,v 1.22 2018/09/02 17:36:57 riastradh Exp $ */
+/* $NetBSD: intel_display.c,v 1.23 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2006-2007 Intel Corporation
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_display.c,v 1.22 2018/09/02 17:36:57 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_display.c,v 1.23 2018/09/13 08:25:55 mrg Exp $");
#include <linux/dmi.h>
#include <linux/module.h>
@@ -5465,7 +5465,7 @@ static void intel_update_max_cdclk(struc
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
if (limit == SKL_DFSM_CDCLK_LIMIT_675)
@@ -9905,7 +9905,7 @@ static void haswell_get_ddi_port_state(s
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_BROXTON(dev))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
@@ -12161,7 +12161,7 @@ static void intel_dump_pipe_config(struc
pipe_config->dpll_hw_state.pll9,
pipe_config->dpll_hw_state.pll10,
pipe_config->dpll_hw_state.pcsdw12);
- } else if (IS_SKYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
pipe_config->ddi_pll_sel,
@@ -14185,7 +14185,7 @@ static void intel_setup_outputs(struct d
*/
found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
/* WaIgnoreDDIAStrap: skl */
- if (found || IS_SKYLAKE(dev))
+ if (found || (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)))
intel_ddi_init(dev, PORT_A);
/* DDI B, C and D detection is indicated by the SFUSE_STRAP
@@ -14201,7 +14201,7 @@ static void intel_setup_outputs(struct d
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
- if (IS_SKYLAKE(dev) &&
+ if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
@@ -14660,7 +14660,7 @@ static void intel_init_display(struct dr
}
/* Returns the core display clock speed */
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
dev_priv->display.get_display_clock_speed =
skylake_get_display_clock_speed;
else if (IS_BROXTON(dev))
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c:1.18 src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c:1.19
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c:1.18 Sun Sep 2 17:36:57 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_dp.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_dp.c,v 1.18 2018/09/02 17:36:57 riastradh Exp $ */
+/* $NetBSD: intel_dp.c,v 1.19 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2008 Intel Corporation
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_dp.c,v 1.18 2018/09/02 17:36:57 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_dp.c,v 1.19 2018/09/13 08:25:55 mrg Exp $");
#include <linux/i2c.h>
#include <linux/slab.h>
@@ -1050,7 +1050,7 @@ intel_dp_aux_init(struct intel_dp *intel
/* On SKL we don't have Aux for port E so we rely on VBT to set
* a proper alternate aux channel.
*/
- if (IS_SKYLAKE(dev) && port == PORT_E) {
+ if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
switch (info->alternate_aux_channel) {
case DP_AUX_B:
porte_aux_ctl_reg = DPB_AUX_CH_CTL;
@@ -1248,7 +1248,7 @@ intel_dp_source_rates(struct drm_device
if (IS_BROXTON(dev)) {
*source_rates = bxt_rates;
size = ARRAY_SIZE(bxt_rates);
- } else if (IS_SKYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
*source_rates = skl_rates;
size = ARRAY_SIZE(skl_rates);
} else {
@@ -1568,7 +1568,7 @@ found:
&pipe_config->dp_m2_n2);
}
- if (IS_SKYLAKE(dev) && is_edp(intel_dp))
+ if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
skl_edp_set_pll_config(pipe_config);
else if (IS_BROXTON(dev))
/* handled in ddi */;
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c:1.3 src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c:1.4
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c:1.3 Mon Aug 27 07:21:33 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_fbc.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_fbc.c,v 1.3 2018/08/27 07:21:33 riastradh Exp $ */
+/* $NetBSD: intel_fbc.c,v 1.4 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2014 Intel Corporation
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_fbc.c,v 1.3 2018/08/27 07:21:33 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_fbc.c,v 1.4 2018/09/13 08:25:55 mrg Exp $");
#include "intel_drv.h"
#include "i915_drv.h"
@@ -586,7 +586,8 @@ static int find_compression_threshold(st
* reserved range size, so it always assumes the maximum (8mb) is used.
* If we enable FBC using a CFB on that memory range we'll get FIFO
* underruns, even if that range is not reserved by the BIOS. */
- if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
+ if (IS_BROADWELL(dev_priv) ||
+ IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024;
else
end = dev_priv->gtt.stolen_usable_size;
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c:1.12 src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c:1.13
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c:1.12 Mon Aug 27 15:09:35 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_guc_loader.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_guc_loader.c,v 1.12 2018/08/27 15:09:35 riastradh Exp $ */
+/* $NetBSD: intel_guc_loader.c,v 1.13 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2014 Intel Corporation
@@ -29,7 +29,7 @@
* Alex Dai <yu....@intel.com>
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_guc_loader.c,v 1.12 2018/08/27 15:09:35 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_guc_loader.c,v 1.13 2018/09/13 08:25:55 mrg Exp $");
#include <linux/firmware.h>
#include <linux/module.h>
@@ -69,6 +69,9 @@ __KERNEL_RCSID(0, "$NetBSD: intel_guc_lo
#define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
+#define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
+MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
+
/* User-friendly representation of an enum */
const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
{
@@ -589,6 +592,10 @@ void intel_guc_ucode_init(struct drm_dev
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = 4;
guc_fw->guc_fw_minor_wanted = 3;
+ } else if (IS_KABYLAKE(dev)) {
+ fw_path = I915_KBL_GUC_UCODE;
+ guc_fw->guc_fw_major_wanted = 9;
+ guc_fw->guc_fw_minor_wanted = 14;
} else {
i915.enable_guc_submission = false;
fw_path = ""; /* unknown device */
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c:1.2 src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c:1.3
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c:1.2 Mon Aug 27 04:58:24 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_mocs.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_mocs.c,v 1.2 2018/08/27 04:58:24 riastradh Exp $ */
+/* $NetBSD: intel_mocs.c,v 1.3 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright (c) 2015 Intel Corporation
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_mocs.c,v 1.2 2018/08/27 04:58:24 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_mocs.c,v 1.3 2018/09/13 08:25:55 mrg Exp $");
#include "intel_mocs.h"
#include "intel_lrc.h"
@@ -148,7 +148,7 @@ static bool get_mocs_settings(struct drm
{
bool result = false;
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c:1.8 src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c:1.9
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c:1.8 Mon Aug 27 07:29:50 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_ringbuffer.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_ringbuffer.c,v 1.8 2018/08/27 07:29:50 riastradh Exp $ */
+/* $NetBSD: intel_ringbuffer.c,v 1.9 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2008-2010 Intel Corporation
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_ringbuffer.c,v 1.8 2018/08/27 07:29:50 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_ringbuffer.c,v 1.9 2018/09/13 08:25:55 mrg Exp $");
#include <asm/param.h>
#include <drm/drmP.h>
@@ -993,7 +993,7 @@ static int gen9_init_workarounds(struct
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
- if (IS_SKYLAKE(dev) ||
+ if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ||
(IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1149,6 +1149,65 @@ static int bxt_init_workarounds(struct i
return 0;
}
+static int kbl_init_workarounds(struct intel_engine_cs *ring)
+{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ ret = gen9_init_workarounds(ring);
+ if (ret)
+ return ret;
+
+ /* WaEnableGapsTsvCreditFix:kbl */
+ I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+ GEN9_GAPS_TSV_CREDIT_DISABLE));
+
+ /* WaDisableDynamicCreditSharing:kbl */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+ WA_SET_BIT(GAMT_CHKN_BIT_REG,
+ GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+
+ /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+ if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FENCE_DEST_SLM_DISABLE);
+
+ /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+ * involving this register should also be added to WA batch as required.
+ */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+ /* WaDisableLSQCROPERFforOCL:kbl */
+ I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_RO_PERF_DIS);
+
+ /* WaToEnableHwFixForPushConstHWBug:kbl */
+ if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
+ /* WaDisableGafsUnitClkGating:kbl */
+ WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaDisableSbeCacheDispatchPortSharing:kbl */
+ WA_SET_BIT_MASKED(
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
+ /* WaInPlaceDecompressionHang:kbl */
+ WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+
+#ifdef notyet
+ /* WaDisableLSQCROPERFforOCL:kbl */
+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
int init_workarounds_ring(struct intel_engine_cs *ring)
{
struct drm_device *dev = ring->dev;
@@ -1170,6 +1229,9 @@ int init_workarounds_ring(struct intel_e
if (IS_BROXTON(dev))
return bxt_init_workarounds(ring);
+ if (IS_KABYLAKE(dev))
+ return kbl_init_workarounds(ring);
+
return 0;
}
Index: src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c
diff -u src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c:1.5 src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c:1.6
--- src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c:1.5 Mon Aug 27 07:30:37 2018
+++ src/sys/external/bsd/drm2/dist/drm/i915/intel_runtime_pm.c Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: intel_runtime_pm.c,v 1.5 2018/08/27 07:30:37 riastradh Exp $ */
+/* $NetBSD: intel_runtime_pm.c,v 1.6 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright © 2012-2014 Intel Corporation
@@ -29,7 +29,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_runtime_pm.c,v 1.5 2018/08/27 07:30:37 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_runtime_pm.c,v 1.6 2018/09/13 08:25:55 mrg Exp $");
#include <linux/pm_runtime.h>
#include <linux/vgaarb.h>
@@ -55,7 +55,7 @@ __KERNEL_RCSID(0, "$NetBSD: intel_runtim
*/
#define GEN9_ENABLE_DC5(dev) 0
-#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
+#define SKL_ENABLE_DC6(dev) (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
#define for_each_power_well(i, power_well, domain_mask, power_domains) \
for (i = 0; \
@@ -493,7 +493,8 @@ static void assert_can_enable_dc5(struct
bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
SKL_DISP_PW_2);
- WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
+ WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
+ "Platform doesn't support DC5.\n");
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
@@ -556,7 +557,8 @@ static void assert_can_enable_dc6(struct
{
struct drm_device *dev = dev_priv->dev;
- WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
+ WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
+ "Platform doesn't support DC6.\n");
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
"Backlight is not disabled.\n");
@@ -686,7 +688,7 @@ static void skl_set_power_well(struct dr
}
} else {
if (enable_requested) {
- if (IS_SKYLAKE(dev) &&
+ if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
(power_well->data == SKL_DISP_PW_1) &&
(intel_csr_load_status_get(dev_priv) == FW_LOADED))
DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
@@ -1848,7 +1850,7 @@ sanitize_disable_power_well_option(const
if (disable_power_well >= 0)
return !!disable_power_well;
- if (IS_SKYLAKE(dev_priv)) {
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
DRM_DEBUG_KMS("Disabling display power well support\n");
return 0;
}
@@ -1891,7 +1893,7 @@ int intel_power_domains_init(struct drm_
set_power_wells(power_domains, hsw_power_wells);
} else if (IS_BROADWELL(dev_priv->dev)) {
set_power_wells(power_domains, bdw_power_wells);
- } else if (IS_SKYLAKE(dev_priv->dev)) {
+ } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
set_power_wells(power_domains, skl_power_wells);
} else if (IS_BROXTON(dev_priv->dev)) {
set_power_wells(power_domains, bxt_power_wells);
Index: src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h
diff -u src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h:1.2 src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h:1.3
--- src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h:1.2 Mon Aug 27 04:58:38 2018
+++ src/sys/external/bsd/drm2/dist/include/drm/i915_pciids.h Thu Sep 13 08:25:55 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i915_pciids.h,v 1.2 2018/08/27 04:58:38 riastradh Exp $ */
+/* $NetBSD: i915_pciids.h,v 1.3 2018/09/13 08:25:55 mrg Exp $ */
/*
* Copyright 2013 Intel Corporation
@@ -285,10 +285,18 @@
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \
+#define INTEL_SKL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
+ INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
+ INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
+
#define INTEL_SKL_IDS(info) \
INTEL_SKL_GT1_IDS(info), \
INTEL_SKL_GT2_IDS(info), \
- INTEL_SKL_GT3_IDS(info)
+ INTEL_SKL_GT3_IDS(info), \
+ INTEL_SKL_GT4_IDS(info)
#define INTEL_BXT_IDS(info) \
INTEL_VGA_DEVICE(0x0A84, info), \
@@ -297,4 +305,40 @@
INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
+#define INTEL_KBL_GT1_IDS(info) \
+ INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
+ INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
+ INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
+ INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
+ INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
+ INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
+
+#define INTEL_KBL_GT2_IDS(info) \
+ INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
+ INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
+ INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
+ INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
+ INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
+
+#define INTEL_KBL_GT3_IDS(info) \
+ INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
+ INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
+ INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
+
+#define INTEL_KBL_GT4_IDS(info) \
+ INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
+ INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
+ INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
+ INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
+
+#define INTEL_KBL_IDS(info) \
+ INTEL_KBL_GT1_IDS(info), \
+ INTEL_KBL_GT2_IDS(info), \
+ INTEL_KBL_GT3_IDS(info), \
+ INTEL_KBL_GT4_IDS(info)
+
#endif /* _I915_PCIIDS_H */
