Module Name: src
Committed By: aymeric
Date: Wed Sep 19 17:31:39 UTC 2018
Added Files:
src/sys/arch/arm/altera: cycv_clkmgr.c cycv_dwcmmc.c cycv_gmac.c
cycv_intr.h cycv_platform.c cycv_reg.h cycv_rstmgr.c cycv_var.h
files.altera
src/sys/arch/arm/dts: socfpga_cyclone5_de0_sockit.dts
src/sys/arch/evbarm/altera: altera_start.S genassym.cf platform.h
src/sys/arch/evbarm/conf: NANOSOC files.altera mk.altera std.altera
Log Message:
Add support for the DE0 NanoSoC board.
It's Cyclone V based and thus includes a dual-core Cortex A9 @925MHz.
Most standard peripherals are supported (USB, SDCard, Ethernet) and
no unusual peripheral is supported yet (FPGA, GPIO, ...)
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/altera/cycv_clkmgr.c \
src/sys/arch/arm/altera/cycv_dwcmmc.c src/sys/arch/arm/altera/cycv_gmac.c \
src/sys/arch/arm/altera/cycv_intr.h \
src/sys/arch/arm/altera/cycv_platform.c \
src/sys/arch/arm/altera/cycv_reg.h src/sys/arch/arm/altera/cycv_rstmgr.c \
src/sys/arch/arm/altera/cycv_var.h src/sys/arch/arm/altera/files.altera
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/dts/socfpga_cyclone5_de0_sockit.dts
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/altera/altera_start.S \
src/sys/arch/evbarm/altera/genassym.cf \
src/sys/arch/evbarm/altera/platform.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/conf/NANOSOC \
src/sys/arch/evbarm/conf/files.altera src/sys/arch/evbarm/conf/mk.altera \
src/sys/arch/evbarm/conf/std.altera
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/arm/altera/cycv_clkmgr.c
diff -u /dev/null src/sys/arch/arm/altera/cycv_clkmgr.c:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_clkmgr.c Wed Sep 19 17:31:38 2018
@@ -0,0 +1,660 @@
+/* $NetBSD: cycv_clkmgr.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+/* This file is in the public domain. */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: cycv_clkmgr.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/atomic.h>
+#include <sys/kmem.h>
+
+#include <dev/clk/clk_backend.h>
+
+#include <arm/altera/cycv_reg.h>
+#include <arm/altera/cycv_var.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#define CYCV_CLOCK_OSC1 25000000
+
+static int cycv_clkmgr_match(device_t, cfdata_t, void *);
+static void cycv_clkmgr_attach(device_t, device_t, void *);
+
+static struct clk *cycv_clkmgr_clock_decode(device_t, int, const void *,
+ size_t);
+
+static const struct fdtbus_clock_controller_func cycv_clkmgr_fdtclock_funcs = {
+ .decode = cycv_clkmgr_clock_decode
+};
+
+static struct clk *cycv_clkmgr_clock_get(void *, const char *);
+static void cycv_clkmgr_clock_put(void *, struct clk *);
+static u_int cycv_clkmgr_clock_get_rate(void *, struct clk *);
+static int cycv_clkmgr_clock_set_rate(void *, struct clk *, u_int);
+static int cycv_clkmgr_clock_enable(void *, struct clk *);
+static int cycv_clkmgr_clock_disable(void *, struct clk *);
+static int cycv_clkmgr_clock_set_parent(void *, struct clk *, struct clk *);
+static struct clk *cycv_clkmgr_clock_get_parent(void *, struct clk *);
+
+static const struct clk_funcs cycv_clkmgr_clock_funcs = {
+ .get = cycv_clkmgr_clock_get,
+ .put = cycv_clkmgr_clock_put,
+ .get_rate = cycv_clkmgr_clock_get_rate,
+ .set_rate = cycv_clkmgr_clock_set_rate,
+ .enable = cycv_clkmgr_clock_enable,
+ .disable = cycv_clkmgr_clock_disable,
+ .get_parent = cycv_clkmgr_clock_get_parent,
+ .set_parent = cycv_clkmgr_clock_set_parent,
+};
+
+struct cycv_clk {
+ struct clk base;
+
+ int id;
+ u_int refcnt;
+
+ struct cycv_clk *parent; /* cached and valid if not NULL */
+ /* parent_id is not zero and filled with dtb if only one parent clock */
+ int parent_id;
+
+ int type;
+#define CYCV_CLK_TYPE_PLL 0x0001
+#define CYCV_CLK_TYPE_FIXED 0x0002
+#define CYCV_CLK_TYPE_FIXED_DIV 0x0003
+#define CYCV_CLK_TYPE_DIV 0x0004
+
+ int flags;
+#define CYCV_CLK_FLAG_HAVE_GATE 0x0001
+#define CYCV_CLK_FLAG_IS_AVAIL 0x0002
+
+ union {
+ bus_addr_t pll_addr;
+ uint32_t fixed_freq;
+ uint32_t fixed_div;
+ struct {
+ bus_addr_t addr;
+ uint32_t mask;
+ int shift;
+ } div;
+ } u;
+
+ bus_addr_t gate_addr;
+ int gate_shift;
+};
+
+struct cycv_clkmgr_softc {
+ device_t sc_dev;
+ struct clk_domain sc_clkdom;
+
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+
+ struct cycv_clk *sc_clocks;
+ u_int sc_nclocks;
+};
+
+static void cycv_clkmgr_init(struct cycv_clkmgr_softc *, int);
+static void cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *, int, u_int);
+static u_int cycv_clkmgr_clocks_traverse(struct cycv_clkmgr_softc *, int,
+ void (*)(struct cycv_clkmgr_softc *, int, u_int), u_int);
+static struct cycv_clk_mux_info *cycv_clkmgr_get_mux_info(const char *);
+static void cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *,
+ struct cycv_clk *);
+
+CFATTACH_DECL_NEW(cycvclkmgr, sizeof (struct cycv_clkmgr_softc),
+ cycv_clkmgr_match, cycv_clkmgr_attach, NULL, NULL);
+
+static int
+cycv_clkmgr_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const char *compatible[] = { "altr,clk-mgr", NULL };
+ struct fdt_attach_args *faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+cycv_clkmgr_attach(device_t parent, device_t self, void *aux)
+{
+ struct cycv_clkmgr_softc *sc = device_private(self);
+ struct fdt_attach_args *faa = aux;
+ int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+ int error;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
+ if (error) {
+ aprint_error(": couldn't map %#llx: %d",
+ (uint64_t) addr, error);
+ return;
+ }
+
+ aprint_normal(": clock manager\n");
+
+ sc->sc_clkdom.funcs = &cycv_clkmgr_clock_funcs;
+ sc->sc_clkdom.priv = sc;
+
+ cycv_clkmgr_init(sc, phandle);
+}
+
+static void
+cycv_clkmgr_init(struct cycv_clkmgr_softc *sc, int clkmgr_handle)
+{
+ int clocks_handle;
+
+ clocks_handle = of_find_firstchild_byname(clkmgr_handle, "clocks");
+ if (clocks_handle == -1) {
+ aprint_error_dev(sc->sc_dev, "no clocks property\n");
+ return;
+ }
+
+ sc->sc_nclocks = cycv_clkmgr_clocks_traverse(sc, clocks_handle, NULL,
+ 0);
+
+ sc->sc_clocks = kmem_zalloc(sc->sc_nclocks * sizeof *sc->sc_clocks,
+ KM_NOSLEEP);
+ if (sc->sc_clocks == NULL) {
+ aprint_error_dev(sc->sc_dev, "no memory\n");
+ sc->sc_nclocks = 0;
+ return;
+ }
+
+ cycv_clkmgr_clocks_traverse(sc, clocks_handle, cycv_clkmgr_clock_parse,
+ 0);
+
+#if 1
+ for (int i = 0; i < sc->sc_nclocks; i++)
+ cycv_clkmgr_clock_print(sc, &sc->sc_clocks[i]);
+#else
+ (void) cycv_clkmgr_clock_print;
+#endif
+}
+
+#define CYCV_CLK_MAX_PARENTS 3
+
+static struct cycv_clk_mux_info {
+ const char *name;
+ const char *parents[CYCV_CLK_MAX_PARENTS];
+ int nparents;
+ bus_addr_t addr;
+ uint32_t mask;
+} cycv_clk_mux_tree[] = {
+ { "periph_pll", { "osc1", "osc2", "f2s_periph_ref_clk" }, 3,
+ 0x80, 0x00c00000 },
+ { "sdram_pll", { "osc1", "osc2", "f2s_sdram_ref_clk" }, 3,
+ 0xc0, 0x00c00000 },
+ { "l4_mp_clk", { "mainclk", "per_base_clk" }, 2, 0x70, 0x00000001 },
+ { "l4_sp_clk", { "mainclk", "per_base_clk" }, 2, 0x70, 0x00000002 },
+ { "sdmmc_clk",
+ { "f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk" },
+ 3, 0xac, 0x00000003 },
+ { "nand_x_clk",
+ { "f2s_periph_ref_clk", "main_nand_sdmmc_clk", "per_nand_mmc_clk" },
+ 3, 0xac, 0x0000000c },
+ { "qspi_clk", { "f2s_periph_ref_clk", "main_qspi_clk", "per_qsi_clk" },
+ 3, 0xac, 0x00000030 },
+
+ /* Don't special case bypass */
+ { "dbg_base_clk", { "main_pll" }, 1, 0, 0 },
+ /* Bug in dtb */
+ { "nand_clk", { "nand_x_clk" }, 1, 0, 0 },
+};
+
+static const char * const cycv_clkmgr_compat_fixed[] = { "fixed-clock", NULL };
+static const char * const cycv_clkmgr_compat_pll[] = { "altr,socfpga-pll-clock",
+ NULL };
+static const char * const cycv_clkmgr_compat_perip[] = {
+ "altr,socfpga-perip-clk",
+ "altr,socfpga-gate-clk",
+ NULL
+};
+
+static void
+cycv_clkmgr_clock_parse(struct cycv_clkmgr_softc *sc, int handle, u_int clkno)
+{
+ struct cycv_clk *clk = &sc->sc_clocks[clkno];
+ int flags = 0;
+ const uint8_t *buf;
+ int len;
+
+ clk->base.domain = &sc->sc_clkdom;
+ clk->base.name = fdtbus_get_string(handle, "name");
+ clk->base.flags = 0;
+
+ clk->id = handle;
+ clk->parent = NULL;
+ clk->parent_id = 0;
+ clk->refcnt = 0;
+
+ if (of_compatible(handle, cycv_clkmgr_compat_fixed) != -1) {
+ clk->type = CYCV_CLK_TYPE_FIXED;
+ if (of_getprop_uint32(handle, "clock-frequency",
+ &clk->u.fixed_freq) == 0) {
+ flags |= CYCV_CLK_FLAG_IS_AVAIL;
+ }
+ } else if (of_compatible(handle, cycv_clkmgr_compat_pll) != -1) {
+ if (fdtbus_get_reg(handle, 0, &clk->u.pll_addr, NULL) != 0)
+ goto err;
+ clk->type = CYCV_CLK_TYPE_PLL;
+ flags |= CYCV_CLK_FLAG_IS_AVAIL;
+ } else if (of_compatible(handle, cycv_clkmgr_compat_perip) != -1) {
+ if (of_getprop_uint32(handle, "fixed-divider",
+ &clk->u.fixed_div) == 0) {
+ clk->type = CYCV_CLK_TYPE_FIXED_DIV;
+ } else if (fdtbus_get_reg(handle, 0, &clk->u.div.addr, NULL) ==
+ 0) {
+ clk->type = CYCV_CLK_TYPE_DIV;
+ clk->u.div.shift = 0;
+ clk->u.div.mask = 0xff;
+ } else if ((buf = fdtbus_get_prop(handle, "div-reg", &len)) !=
+ NULL) {
+ if (len != 3 * 4)
+ goto err;
+
+ clk->type = CYCV_CLK_TYPE_DIV;
+ clk->u.div.addr = of_decode_int(buf);
+ clk->u.div.shift = of_decode_int(buf + 4);
+ clk->u.div.mask = ((1 << of_decode_int(buf + 8)) - 1) <<
+ clk->u.div.shift;
+ } else {
+ /* Simply a gate and/or a mux */
+ clk->type = CYCV_CLK_TYPE_FIXED_DIV;
+ clk->u.fixed_div = 1;
+ }
+ flags |= CYCV_CLK_FLAG_IS_AVAIL;
+ } else
+ goto err;
+
+ if ((buf = fdtbus_get_prop(handle, "clk-gate", &len)) != NULL) {
+ clk->gate_addr = of_decode_int(buf);
+ clk->gate_shift = of_decode_int(buf + 4);
+ flags |= CYCV_CLK_FLAG_HAVE_GATE;
+ }
+
+ buf = fdtbus_get_prop(handle, "clocks", &len);
+ if (buf != NULL && len == sizeof (uint32_t)) {
+ clk->parent_id =
+ fdtbus_get_phandle_from_native(of_decode_int(buf));
+ }
+
+ clk->flags = flags;
+
+ fdtbus_register_clock_controller(sc->sc_dev, handle,
+ &cycv_clkmgr_fdtclock_funcs);
+
+ return;
+err:
+ aprint_debug_dev(sc->sc_dev, "(%s) error parsing phandle %d\n",
+ clk->base.name, handle);
+}
+
+static u_int
+cycv_clkmgr_clocks_traverse(struct cycv_clkmgr_softc *sc, int clocks_handle,
+ void func(struct cycv_clkmgr_softc *, int, u_int),
+ u_int nclocks)
+{
+ int clk_handle;
+
+ for (clk_handle = OF_child(clocks_handle); clk_handle != 0;
+ clk_handle = OF_peer(clk_handle)) {
+ if (func != NULL)
+ func(sc, clk_handle, nclocks);
+ nclocks++;
+
+ nclocks = cycv_clkmgr_clocks_traverse(sc, clk_handle, func,
+ nclocks);
+ }
+
+ return nclocks;
+}
+
+static struct cycv_clk_mux_info *
+cycv_clkmgr_get_mux_info(const char *name) {
+ size_t i;
+
+ for (i = 0; i < __arraycount(cycv_clk_mux_tree); i++) {
+ struct cycv_clk_mux_info *cand = &cycv_clk_mux_tree[i];
+ if (strncmp(name, cand->name, strlen(cand->name)) == 0)
+ return cand;
+ }
+
+ return NULL;
+}
+
+static struct cycv_clk *
+cycv_clkmgr_clock_lookup_by_id(struct cycv_clkmgr_softc *sc, int id)
+{
+ size_t i;
+
+ for (i = 0; i < sc->sc_nclocks; i++) {
+ if (sc->sc_clocks[i].id == id)
+ return &sc->sc_clocks[i];
+ }
+
+ return NULL;
+}
+
+static struct cycv_clk *
+cycv_clkmgr_clock_lookup_by_name(struct cycv_clkmgr_softc *sc, const char *name)
+{
+ size_t i;
+
+ for (i = 0; i < sc->sc_nclocks; i++) {
+ struct cycv_clk *cand = &sc->sc_clocks[i];
+ if (strncmp(cand->base.name, name, strlen(name)) == 0)
+ return cand;
+ }
+
+ return NULL;
+}
+
+static void
+cycv_clkmgr_clock_print(struct cycv_clkmgr_softc *sc, struct cycv_clk *clk) {
+ uint32_t numer;
+ uint32_t denom;
+ uint32_t tmp;
+
+ aprint_debug("clock %s, id %d, frequency %uHz:\n", clk->base.name,
+ clk->id, cycv_clkmgr_clock_get_rate(sc, &clk->base));
+ if (clk->parent != NULL)
+ aprint_debug("parent: %s", clk->parent->base.name);
+ else
+ aprint_debug("parent_id: %d", clk->parent_id);
+ aprint_debug(", flags: %d\n", clk->flags);
+ switch (clk->type) {
+ case CYCV_CLK_TYPE_PLL:
+ tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);
+ numer = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1;
+ denom = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1;
+ aprint_debug(" PLL num = %u, den = %u\n", numer, denom);
+ break;
+ case CYCV_CLK_TYPE_FIXED:
+ aprint_debug(" Fixed frequency = %u\n", clk->u.fixed_freq);
+ break;
+ case CYCV_CLK_TYPE_FIXED_DIV:
+ aprint_debug(" Fixed divisor = %u\n", clk->u.fixed_div);
+ break;
+ case CYCV_CLK_TYPE_DIV:
+ tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.div.addr);
+ tmp = (tmp & clk->u.div.mask) >> clk->u.div.shift;
+ if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
+ tmp += 1;
+ else
+ tmp = (1 << tmp);
+ aprint_debug(" Divisor = %u\n", tmp);
+ break;
+ default:
+ aprint_debug(" Unknown!!!\n");
+ break;
+ }
+
+ if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {
+ tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr);
+ tmp &= (1 << clk->gate_shift);
+ aprint_debug(" Gate %s\n", tmp? "on" : "off");
+ }
+
+
+}
+
+static struct clk *
+cycv_clkmgr_clock_decode(device_t dev, int cc_phandle, const void *data,
+ size_t len)
+{
+ struct cycv_clkmgr_softc *sc = device_private(dev);
+ struct cycv_clk *clk;
+
+ if (data != NULL || len != 0) {
+ aprint_debug_dev(dev, "can't decode clock entry\n");
+ return NULL;
+ }
+
+ clk = cycv_clkmgr_clock_lookup_by_id(sc, cc_phandle);
+
+ return clk == NULL? NULL : &clk->base;
+}
+
+static struct clk *
+cycv_clkmgr_clock_get(void *priv, const char *name)
+{
+ aprint_debug("%s: called and not implemented\n", __func__);
+ (void) cycv_clkmgr_get_mux_info;
+ (void) cycv_clkmgr_clock_lookup_by_name;
+
+ return NULL;
+}
+
+static void
+cycv_clkmgr_clock_put(void *priv, struct clk *clk)
+{
+ aprint_debug("%s: called and not implemented\n", __func__);
+}
+
+static u_int
+cycv_clkmgr_clock_get_rate(void *priv, struct clk *base_clk)
+{
+ struct cycv_clkmgr_softc *sc = priv;
+ struct cycv_clk *clk = (struct cycv_clk *) base_clk;
+ struct cycv_clk *parent;
+ uint32_t parent_rate = 0;
+ uint32_t divisor = 0;
+ uint32_t numer;
+ uint32_t tmp;
+
+ if (clk->type == CYCV_CLK_TYPE_FIXED)
+ return clk->u.fixed_freq;
+
+ parent = (struct cycv_clk *)
+ cycv_clkmgr_clock_get_parent(priv, base_clk);
+ if (parent == NULL) {
+ aprint_debug_dev(sc->sc_dev, "can't get parent of clock %s\n",
+ clk->base.name);
+ return 0;
+ }
+ parent_rate = cycv_clkmgr_clock_get_rate(priv, &parent->base);
+
+ if (strncmp(clk->base.name, "mpuclk@", strlen("mpuclk@")) == 0)
+ parent_rate /= 2;
+ else if (strncmp(clk->base.name, "mainclk@", strlen("mainclk@")) == 0)
+ parent_rate /= 4;
+ else if (strncmp(clk->base.name, "dbgatclk@", strlen("dbgatclk@")) == 0)
+ parent_rate /= 4;
+
+ switch (clk->type) {
+ case CYCV_CLK_TYPE_FIXED_DIV:
+ return parent_rate / clk->u.fixed_div;
+
+ case CYCV_CLK_TYPE_DIV:
+ divisor = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ clk->u.div.addr);
+ divisor = (divisor & clk->u.div.mask) >> clk->u.div.shift;
+ if (__SHIFTOUT_MASK(clk->u.div.mask) > 0xf)
+ divisor += 1;
+ else
+ divisor = (1 << divisor);
+
+ return parent_rate / divisor;
+
+ case CYCV_CLK_TYPE_PLL:
+ tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, clk->u.pll_addr);
+ numer = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1;
+ divisor = __SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1;
+
+ return (uint64_t) parent_rate * numer / divisor;
+ }
+
+ aprint_debug_dev(sc->sc_dev, "unknown clock type %d\n", clk->type);
+
+ return 0;
+}
+
+static int
+cycv_clkmgr_clock_set_rate(void *priv, struct clk *clk, u_int rate)
+{
+ aprint_debug("%s: called and not implemented\n", __func__);
+ return EINVAL;
+}
+
+static int
+cycv_clkmgr_clock_set(void *priv, struct clk *base_clk, int val) {
+ struct cycv_clkmgr_softc *sc = priv;
+ struct cycv_clk *clk = (struct cycv_clk *) base_clk;
+
+ if (clk->flags & CYCV_CLK_FLAG_HAVE_GATE) {
+ uint32_t tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
+ clk->gate_addr);
+ tmp &= ~(1 << clk->gate_shift);
+ tmp |= val << clk->gate_shift;
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, clk->gate_addr, tmp);
+ } else
+ /* XXX should iterate to the root of the clock domain */
+ return 0;
+
+ return 0;
+}
+
+static int
+cycv_clkmgr_clock_enable(void *priv, struct clk *clk)
+{
+ return cycv_clkmgr_clock_set(priv, clk, 1);
+}
+
+static int
+cycv_clkmgr_clock_disable(void *priv, struct clk *clk)
+{
+ return cycv_clkmgr_clock_set(priv, clk, 0);
+}
+
+static int
+cycv_clkmgr_clock_set_parent(void *priv, struct clk *clk,
+ struct clk *clk_parent)
+{
+ /* lookup clk in muxinfo table */
+ /* if not found, parent is not settable */
+ /* check if clk_parent can be a parent (by name) */
+ /* beware of special case where there is only one parent in mux */
+ /* enact reparenting h/w wise, update clk->parent */
+ aprint_debug("%s: called and not implemented\n", __func__);
+ return EINVAL;
+}
+
+static struct clk *
+cycv_clkmgr_clock_get_parent(void *priv, struct clk *base_clk)
+{
+ struct cycv_clkmgr_softc *sc = priv;
+ struct cycv_clk *clk = (struct cycv_clk *) base_clk;
+ struct cycv_clk_mux_info *mux;
+ struct cycv_clk *parent = clk->parent;
+ int parent_index;
+ uint32_t tmp;
+
+ if (parent != NULL)
+ goto update;
+
+ if (clk->parent_id != 0) {
+ parent = cycv_clkmgr_clock_lookup_by_id(sc, clk->parent_id);
+ goto update;
+ }
+
+ mux = cycv_clkmgr_get_mux_info(clk->base.name);
+
+ if (mux == NULL)
+ goto update;
+
+ if (mux->nparents == 1)
+ parent_index = 0;
+ else {
+ tmp = bus_space_read_4(sc->sc_bst, sc->sc_bsh, mux->addr);
+ parent_index = __SHIFTOUT(tmp, mux->mask);
+ }
+
+ if (parent_index >= mux->nparents) {
+ aprint_error_dev(sc->sc_dev,
+ "clock %s parent has non existent index %d\n",
+ clk->base.name, parent_index);
+ goto update;
+ }
+
+ parent = cycv_clkmgr_clock_lookup_by_name(sc,
+ mux->parents[parent_index]);
+
+update:
+ clk->parent = parent;
+ return &parent->base;
+}
+
+/*
+ * Functions called during early startup, possibly before autoconfiguration.
+ */
+
+uint32_t
+cycv_clkmgr_early_get_mpu_clk(void) {
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t tmp;
+ uint64_t vco;
+
+ bus_space_map(bst, CYCV_CLKMGR_BASE, CYCV_CLKMGR_SIZE, 0, &bsh);
+
+ tmp = bus_space_read_4(bst, bsh, CYCV_CLKMGR_MAIN_PLL_VCO);
+ vco = (uint64_t) CYCV_CLOCK_OSC1 *
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);
+ tmp = bus_space_read_4(bst, bsh, CYCV_CLKMGR_MAIN_PLL_MPUCLK);
+
+ return vco / 2 / (__SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT) + 1);
+}
+
+uint32_t
+cycv_clkmgr_early_get_l4_sp_clk(void) {
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t tmp;
+ uint32_t res;
+ uint64_t vco;
+
+ bus_space_map(bst, CYCV_CLKMGR_BASE, CYCV_CLKMGR_SIZE, 0, &bsh);
+
+ tmp = bus_space_read_4(bst, bsh, CYCV_CLKMGR_MAIN_PLL_L4SRC);
+ if (__SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_L4SRC_L4SP) == 0) {
+ /* L4 SP clock driven by main clock */
+ vco = (uint64_t) CYCV_CLOCK_OSC1 *
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);
+ tmp = bus_space_read_4(bst, bsh, CYCV_CLKMGR_MAIN_PLL_MAINCLK);
+ tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MAINCLK_CNT);
+
+ res = vco / 4 / (tmp + 1);
+ } else {
+ /* L4 SP clock driven by periph clock */
+ vco = (uint64_t) CYCV_CLOCK_OSC1 *
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_NUMER) + 1) /
+ (__SHIFTOUT(tmp, CYCV_CLKMGR_PLL_VCO_DENOM) + 1);
+ tmp = bus_space_read_4(bst, bsh,
+ CYCV_CLKMGR_PERI_PLL_PERBASECLK);
+ tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_PERI_PLL_PERBASECLK_CNT);
+
+ res = vco / (tmp + 1);
+ }
+
+ tmp = bus_space_read_4(bst, bsh, CYCV_CLKMGR_MAIN_PLL_MAINDIV);
+ tmp = __SHIFTOUT(tmp, CYCV_CLKMGR_MAIN_PLL_MAINDIV_L4SP);
+
+ printf("%s: returning %u\n", __func__, (uint32_t)
+ (res / (1 << tmp)));
+ return res / (1 << tmp);
+}
Index: src/sys/arch/arm/altera/cycv_dwcmmc.c
diff -u /dev/null src/sys/arch/arm/altera/cycv_dwcmmc.c:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_dwcmmc.c Wed Sep 19 17:31:38 2018
@@ -0,0 +1,163 @@
+/* $NetBSD: cycv_dwcmmc.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: cycv_dwcmmc.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <dev/ic/dwc_mmc_reg.h>
+#include <dev/ic/dwc_mmc_var.h>
+#include <dev/fdt/fdtvar.h>
+
+#define FIFO_REG 0x200
+
+static int cycv_dwcmmc_match(device_t, cfdata_t, void *);
+static void cycv_dwcmmc_attach(device_t, device_t, void *);
+
+static int cycv_dwcmmc_card_detect(struct dwc_mmc_softc *);
+
+struct cycv_dwcmmc_softc {
+ struct dwc_mmc_softc sc;
+ struct clk *sc_clk_biu;
+ struct clk *sc_clk_ciu;
+};
+
+CFATTACH_DECL_NEW(cycv_dwcmmc, sizeof(struct dwc_mmc_softc),
+ cycv_dwcmmc_match, cycv_dwcmmc_attach, NULL, NULL);
+
+static const char * const cycv_dwcmmc_compat[] = {
+ "altr,socfpga-dw-mshc",
+ NULL
+};
+
+static int
+cycv_dwcmmc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, cycv_dwcmmc_compat);
+}
+
+static void
+cycv_dwcmmc_attach(device_t parent, device_t self, void *aux)
+{
+ struct cycv_dwcmmc_softc *esc = device_private(self);
+ struct dwc_mmc_softc *sc = &esc->sc;
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ char intrstr[128];
+ bus_addr_t addr;
+ bus_size_t size;
+ u_int fifo_depth;
+ int error;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ if (of_getprop_uint32(phandle, "fifo-depth", &fifo_depth)) {
+ fifo_depth = 64;
+ }
+
+ esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu");
+ if (esc->sc_clk_biu == NULL) {
+ aprint_error(": couldn't get clock biu\n");
+ return;
+ }
+ esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu");
+ if (esc->sc_clk_ciu == NULL) {
+ aprint_error(": couldn't get clock ciu\n");
+ return;
+ }
+
+ error = clk_enable(esc->sc_clk_biu);
+ if (error) {
+ aprint_error(": couldn't enable clock biu: %d\n", error);
+ return;
+ }
+ error = clk_enable(esc->sc_clk_ciu);
+ if (error) {
+ aprint_error(": couldn't enable clock ciu: %d\n", error);
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ sc->sc_dmat = faa->faa_dmat;
+ error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
+ if (error) {
+ aprint_error(": couldn't map %#llx: %d\n",
+ (uint64_t)addr, error);
+ return;
+ }
+
+ sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu);
+ sc->sc_fifo_depth = fifo_depth;
+ sc->sc_fifo_reg = FIFO_REG;
+ sc->sc_flags = DWC_MMC_F_USE_HOLD_REG | DWC_MMC_F_DMA;
+
+ sc->sc_card_detect = cycv_dwcmmc_card_detect;
+ sc->sc_write_protect = NULL;
+
+ aprint_naive("\n");
+ aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq);
+
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error_dev(self, "failed to decode interrupt\n");
+ return;
+ }
+
+ if (dwc_mmc_init(sc) != 0)
+ return;
+
+ sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0,
+ dwc_mmc_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "couldn't establish interrupt on %s\n",
+ intrstr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+}
+
+static int
+cycv_dwcmmc_card_detect(struct dwc_mmc_softc *sc)
+{
+ /* Card detection is broken on the nanosoc. Pretend it's present. */
+
+ return 0;
+}
Index: src/sys/arch/arm/altera/cycv_gmac.c
diff -u /dev/null src/sys/arch/arm/altera/cycv_gmac.c:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_gmac.c Wed Sep 19 17:31:38 2018
@@ -0,0 +1,143 @@
+/* $NetBSD: cycv_gmac.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+/*-
+ * Copyright (c) 2017 Jared McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Taken from sunxi_gmac.c */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(0, "$NetBSD: cycv_gmac.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/gpio.h>
+
+#include <net/if.h>
+#include <net/if_ether.h>
+#include <net/if_media.h>
+
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/dwc_gmac_var.h>
+#include <dev/ic/dwc_gmac_reg.h>
+
+#include <dev/fdt/fdtvar.h>
+
+static const char * compatible[] = { "altr,socfpga-stmmac", NULL };
+
+static int
+cycv_gmac_intr(void *arg)
+{
+ return dwc_gmac_intr(arg);
+}
+
+static int
+cycv_gmac_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct fdt_attach_args * const faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+cycv_gmac_attach(device_t parent, device_t self, void *aux)
+{
+ struct dwc_gmac_softc * const sc = device_private(self);
+ struct fdt_attach_args * const faa = aux;
+ const int phandle = faa->faa_phandle;
+ struct clk *clk_gmac;
+ struct fdtbus_reset *rst_gmac;
+ const char *phy_mode;
+ char intrstr[128];
+ bus_addr_t addr;
+ bus_size_t size;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+ sc->sc_dmat = faa->faa_dmat;
+
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof intrstr)) {
+ aprint_error(": failed to decode interrupt\n");
+ return;
+ }
+
+ clk_gmac = fdtbus_clock_get(phandle, "stmmaceth");
+ if (clk_gmac == NULL) {
+ aprint_error(": couldn't get clock\n");
+ return;
+ }
+
+ rst_gmac = fdtbus_reset_get(phandle, "stmmaceth");
+ if (rst_gmac == NULL) {
+ aprint_error(": couldn't get reset\n");
+ return;
+ }
+
+ phy_mode = fdtbus_get_string(phandle, "phy-mode");
+ if (phy_mode == NULL) {
+ aprint_error(": missing 'phy-mode' property\n");
+ return;
+ }
+
+ if (clk_enable(clk_gmac) != 0) {
+ aprint_error(": couldn't enable clocks\n");
+ return;
+ }
+
+ if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) {
+ aprint_error(": couldn't de-assert reset\n");
+ return;
+ }
+
+ aprint_naive("\n");
+ aprint_normal(": GMAC\n");
+
+ if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0,
+ cycv_gmac_intr, sc) == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt on %s\n",
+ intrstr);
+ return;
+ }
+ aprint_normal_dev(self, "interrupting on %s\n", intrstr);
+
+ dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102);
+}
+
+CFATTACH_DECL_NEW(cycv_gmac, sizeof(struct dwc_gmac_softc),
+ cycv_gmac_match, cycv_gmac_attach, NULL, NULL);
Index: src/sys/arch/arm/altera/cycv_intr.h
diff -u /dev/null src/sys/arch/arm/altera/cycv_intr.h:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_intr.h Wed Sep 19 17:31:38 2018
@@ -0,0 +1,5 @@
+/* $NetBSD: cycv_intr.h,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+#include <arm/fdt/fdt_intr.h>
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h>
Index: src/sys/arch/arm/altera/cycv_platform.c
diff -u /dev/null src/sys/arch/arm/altera/cycv_platform.c:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_platform.c Wed Sep 19 17:31:38 2018
@@ -0,0 +1,145 @@
+/* $NetBSD: cycv_platform.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+/* This file is in the public domain. */
+
+#include "arml2cc.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <arm/altera/cycv_reg.h>
+#include <arm/altera/cycv_var.h>
+#include <arm/cortex/a9tmr_var.h>
+#include <arm/cortex/pl310_var.h>
+#include <arm/cortex/scu_reg.h>
+
+#include <arm/bootconfig.h>
+#include <arm/cpufunc.h>
+
+#include <arm/fdt/arm_fdtvar.h>
+#include <dev/fdt/fdtvar.h>
+
+static void cycv_platform_early_putchar(char);
+
+static const struct pmap_devmap *
+cycv_platform_devmap(void) {
+ static const struct pmap_devmap devmap[] = {
+ DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE,
+ CYCV_PERIPHERAL_BASE,
+ CYCV_PERIPHERAL_SIZE),
+ DEVMAP_ENTRY_END
+ };
+
+ return devmap;
+}
+
+extern void cortex_mpstart(void);
+
+static void
+cycv_platform_bootstrap(void) {
+ uint32_t startfunc = (uint32_t) cortex_mpstart;
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh_l2c;
+ bus_space_handle_t bsh_rst;
+ bus_space_handle_t bsh_scu;
+
+ bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c);
+ bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst);
+ bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu);
+
+ /* Enable Snoop Control Unit */
+ bus_space_write_4(bst, bsh_rst, SCU_CTL,
+ bus_space_read_4(bst, bsh_rst, SCU_CTL) | SCU_CTL_SCU_ENA);
+
+#if NARML2CC > 0
+ arml2cc_init(bst, bsh_l2c, 0);
+#endif
+
+ /*
+ * We place a "B cortex_mpstart" at address 0 in order to bootstrap
+ * CPU 1. We can't use the similar feature of the Boot ROM because
+ * it was unmapped by u-boot in favor of the SDRAM. Plus the dtb is
+ * stored very low in RAM so we can't re-map the Boot ROM easily.
+ */
+
+ *(volatile uint32_t *) 0x0 = 0xea000000 | ((startfunc - 8 - 0x0) >> 2);
+
+ arm_cpu_max = 2;
+
+ arm_dsb();
+
+ armv7_dcache_wbinv_all();
+
+ bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST,
+ bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) &
+ ~CYCV_RSTMGR_MPUMODRST_CPU1);
+}
+
+static void
+cycv_platform_init_attach_args(struct fdt_attach_args *faa) {
+ faa->faa_bst = &armv7_generic_bs_tag;
+ faa->faa_a4x_bst = &armv7_generic_a4x_bs_tag;
+ faa->faa_dmat = &arm_generic_dma_tag;
+}
+
+static void
+cycv_platform_early_putchar(char c) {
+#ifdef CONSADDR
+#define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE)
+ volatile uint32_t *uartaddr = (volatile uint32_t *) CONSADDR_VA;
+
+ while ((uartaddr[com_lsr] & LSR_TXRDY) == 0)
+ ;
+
+ uartaddr[com_data] = c;
+#endif
+}
+
+static void
+cycv_platform_device_register(device_t dev, void *aux) {
+ prop_dictionary_t dict = device_properties(dev);
+
+ if (device_is_a(dev, "arma9tmr")) {
+ prop_dictionary_set_uint32(dict, "frequency",
+ cycv_clkmgr_early_get_mpu_clk() / 4);
+ }
+}
+
+static void
+cycv_platform_reset(void) {
+ bus_space_tag_t bst = &armv7_generic_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t val;
+
+ bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh);
+ val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL);
+ bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL,
+ val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ);
+}
+
+static u_int
+cycv_platform_uart_freq(void) {
+ return cycv_clkmgr_early_get_l4_sp_clk();
+}
+
+static const struct arm_platform cycv_platform = {
+ .ap_devmap = cycv_platform_devmap,
+ .ap_bootstrap = cycv_platform_bootstrap,
+ .ap_init_attach_args = cycv_platform_init_attach_args,
+ .ap_early_putchar = cycv_platform_early_putchar,
+ .ap_device_register = cycv_platform_device_register,
+ .ap_reset = cycv_platform_reset,
+ .ap_delay = a9tmr_delay,
+ .ap_uart_freq = cycv_platform_uart_freq,
+};
+
+ARM_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform);
Index: src/sys/arch/arm/altera/cycv_reg.h
diff -u /dev/null src/sys/arch/arm/altera/cycv_reg.h:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_reg.h Wed Sep 19 17:31:38 2018
@@ -0,0 +1,117 @@
+/* $NetBSD: cycv_reg.h,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+#ifndef _ARM_ALTERA_CYCV_REG_H
+#define _ARM_ALTERA_CYCV_REG_H
+
+#define CYCV_SDRAM_BASE 0x0
+
+#define CYCV_PERIPHERAL_BASE 0xFC000000
+#define CYCV_PERIPHERAL_SIZE (64 * 1024 * 1024)
+
+#define CYCV_PERIPHERAL_VBASE CYCV_PERIPHERAL_BASE
+
+/* Clock manager */
+
+#define CYCV_CLKMGR_BASE 0xFFD04000
+#define CYCV_CLKMGR_SIZE 0x1000
+
+#define CYCV_CLKMGR_CTRL 0x00
+#define CYCV_CLKMGR_CTRL_SAFEMODE __BIT(0)
+#define CYCV_CLKMGR_CTRL_ENSFMDWR __BIT(2)
+
+#define CYCV_CLKMGR_BYPASS 0x04
+#define CYCV_CLKMGR_BYPASS_MAINPLL __BIT(0)
+#define CYCV_CLKMGR_BYPASS_SDRPLL __BIT(1)
+#define CYCV_CLKMGR_BYPASS_SDRPLLSRC __BIT(2)
+#define CYCV_CLKMGR_BYPASS_PERPLL __BIT(3)
+#define CYCV_CLKMGR_BYPASS_PERPLLSRC __BIT(4)
+
+#define CYCV_CLKMGR_INTER 0x08
+#define CYCV_CLKMGR_INT_MAINPLLACHIEVED __BIT(0)
+#define CYCV_CLKMGR_INT_PERPLLACHIEVED __BIT(1)
+#define CYCV_CLKMGR_INT_SDRPLLACHIEVED __BIT(2)
+#define CYCV_CLKMGR_INT_MAINPLLLOST __BIT(3)
+#define CYCV_CLKMGR_INT_PERPLLLOST __BIT(4)
+#define CYCV_CLKMGR_INT_SDRPLLLOST __BIT(5)
+#define CYCV_CLKMGR_INTER_MAINPLLLOCKED __BIT(6)
+#define CYCV_CLKMGR_INTER_PERPLLLOCKED __BIT(7)
+#define CYCV_CLKMGR_INTER_SDRPLLLOCKED __BIT(8)
+
+#define CYCV_CLKMGR_INTREN 0x0C
+/* See CYCV_CLKMGR_INT_* above */
+
+#define CYCV_CLKMGR_DBCTRL 0x10
+#define CYCV_CLKMGR_STAT 0x14
+
+#define CYCV_CLKMGR_MAIN_PLL_VCO 0x40
+#define CYCV_CLKMGR_PLL_VCO_NUMER __BITS(3, 15)
+#define CYCV_CLKMGR_PLL_VCO_DENOM __BITS(16, 21)
+#define CYCV_CLKMGR_MAIN_PLL_MISC 0x44
+#define CYCV_CLKMGR_MAIN_PLL_MPUCLK 0x48
+#define CYCV_CLKMGR_MAIN_PLL_MPUCLK_CNT __BITS(0, 8)
+#define CYCV_CLKMGR_MAIN_PLL_MAINCLK 0x4C
+#define CYCV_CLKMGR_MAIN_PLL_MAINCLK_CNT __BITS(0, 8)
+#define CYCV_CLKMGR_MAIN_PLL_DBGATCLK 0x50
+#define CYCV_CLKMGR_MAIN_PLL_MAINQSPICLK 0x54
+#define CYCV_CLKMGR_MAIN_PLL_MAINNANDSDMMCCLK 0x58
+#define CYCV_CLKMGR_MAIN_PLL_CFGS2FUSER0CLK 0x5C
+#define CYCV_CLKMGR_MAIN_PLL_EN 0x60
+#define CYCV_CLKMGR_MAIN_PLL_MAINDIV 0x64
+#define CYCV_CLKMGR_MAIN_PLL_MAINDIV_L4SP __BITS(7, 9)
+#define CYCV_CLKMGR_MAIN_PLL_DBGDIV 0x68
+#define CYCV_CLKMGR_MAIN_PLL_TRACEDIV 0x6C
+#define CYCV_CLKMGR_MAIN_PLL_L4SRC 0x70
+#define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4SP __BIT(1)
+#define CYCV_CLKMGR_MAIN_PLL_L4SRC_L4MP __BIT(0)
+#define CYCV_CLKMGR_MAIN_PLL_STAT 0x74
+
+#define CYCV_CLKMGR_PERI_PLL_VCO 0x80
+#define CYCV_CLKMGR_PERI_PLL_MISC 0x84
+#define CYCV_CLKMGR_PERI_PLL_EMAC0CLK 0x88
+#define CYCV_CLKMGR_PERI_PLL_EMAC1CLK 0x8C
+#define CYCV_CLKMGR_PERI_PLL_PERQSPICLK 0x90
+#define CYCV_CLKMGR_PERI_PLL_PERNANDSDMMCCLK 0x94
+#define CYCV_CLKMGR_PERI_PLL_PERBASECLK 0x98
+#define CYCV_CLKMGR_PERI_PLL_PERBASECLK_CNT __BITS(0, 8)
+#define CYCV_CLKMGR_PERI_PLL_H2FUSER1CLK 0x9C
+#define CYCV_CLKMGR_PERI_PLL_EN 0xA0
+#define CYCV_CLKMGR_PERI_PLL_DIV 0xA4
+#define CYCV_CLKMGR_PERI_PLL_GPIODIV 0xA8
+#define CYCV_CLKMGR_PERI_PLL_SRC 0xAC
+#define CYCV_CLKMGR_PERI_PLL_STAT 0xB0
+
+#define CYCV_CLKMGR_SDRAM_PLL_VCO 0xC0
+#define CYCV_CLKMGR_SDRAM_PLL_CTRL 0xC4
+#define CYCV_CLKMGR_SDRAM_PLL_DDRDQSCLK 0xC8
+#define CYCV_CLKMGR_SDRAM_PLL_DDR2XDQSCLK 0xCC
+#define CYCV_CLKMGR_SDRAM_PLL_DDRDQCLK 0xD0
+#define CYCV_CLKMGR_SDRAM_PLL_S2FUSER2CLK 0xD4
+#define CYCV_CLKMGR_SDRAM_PLL_EN 0xD8
+#define CYCV_CLKMGR_SDRAM_PLL_STAT 0xDC
+
+/* Reset manager */
+
+#define CYCV_RSTMGR_BASE 0xFFD05000
+#define CYCV_RSTMGR_SIZE 0x24
+
+#define CYCV_RSTMGR_STAT 0x00
+#define CYCV_RSTMGR_CTRL 0x04
+#define CYCV_RSTMGR_CTRL_SWCOLDRSTREQ __BIT(0)
+#define CYCV_RSTMGR_COUNTS 0x08
+#define CYCV_RSTMGR_MPUMODRST 0x10
+#define CYCV_RSTMGR_MPUMODRST_CPU1 __BIT(1)
+#define CYCV_RSTMGR_PERMODRST 0x14
+#define CYCV_RSTMGR_PER2MODRST 0x18
+#define CYCV_RSTMGR_BRGMODRST 0x1C
+#define CYCV_RSTMGR_MISCMODRST 0x20
+
+/* Snoop Control Unit */
+
+#define CYCV_SCU_BASE 0xFFFEC000
+#define CYCV_SCU_SIZE 0x100
+
+/* Level 2 Cache */
+
+#define CYCV_L2CACHE_BASE 0xFFFEF000
+#define CYCV_L2CACHE_SIZE 0x1000
+
+#endif /* _ARM_ALTERA_CYCV_REG_H */
Index: src/sys/arch/arm/altera/cycv_rstmgr.c
diff -u /dev/null src/sys/arch/arm/altera/cycv_rstmgr.c:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_rstmgr.c Wed Sep 19 17:31:38 2018
@@ -0,0 +1,147 @@
+/* $NetBSD: cycv_rstmgr.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+/* This file is in the public domain. */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: cycv_rstmgr.c,v 1.1 2018/09/19 17:31:38 aymeric Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/atomic.h>
+#include <sys/kmem.h>
+
+#include <arm/altera/cycv_reg.h>
+#include <arm/altera/cycv_var.h>
+
+#include <dev/fdt/fdtvar.h>
+
+static int cycv_rstmgr_match(device_t, cfdata_t, void *);
+static void cycv_rstmgr_attach(device_t, device_t, void *);
+
+static void *cycv_rst_acquire(device_t, const void *, size_t);
+static void cycv_rst_release(device_t, void *);
+static int cycv_rst_reset_assert(device_t, void *);
+static int cycv_rst_reset_deassert(device_t, void *);
+
+static const struct fdtbus_reset_controller_func cycv_rstmgr_funcs = {
+ cycv_rst_acquire, cycv_rst_release,
+ cycv_rst_reset_assert, cycv_rst_reset_deassert
+};
+
+struct cycv_rstmgr_softc {
+ device_t sc_dev;
+
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+};
+
+struct cycv_reset {
+ bus_addr_t address;
+ uint32_t mask;
+};
+
+CFATTACH_DECL_NEW(cycvrstmgr, sizeof (struct cycv_rstmgr_softc),
+ cycv_rstmgr_match, cycv_rstmgr_attach, NULL, NULL);
+
+static struct cycv_rstmgr_softc *cycv_rstmgr_sc;
+
+static int
+cycv_rstmgr_match(device_t parent, cfdata_t cf, void *aux)
+{
+ const char *compatible[] = { "altr,rst-mgr", NULL };
+ struct fdt_attach_args *faa = aux;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+cycv_rstmgr_attach(device_t parent, device_t self, void *aux)
+{
+ struct cycv_rstmgr_softc *sc = device_private(self);
+ struct fdt_attach_args *faa = aux;
+ int phandle = faa->faa_phandle;
+ bus_addr_t addr;
+ bus_size_t size;
+ int error;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_bst = faa->faa_bst;
+ error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
+ if (error) {
+ aprint_error(": couldn't map %#llx: %d",
+ (uint64_t) addr, error);
+ return;
+ }
+
+ aprint_normal(": reset manager\n");
+
+ fdtbus_register_reset_controller(self, phandle, &cycv_rstmgr_funcs);
+ cycv_rstmgr_sc = sc;
+}
+
+static void *
+cycv_rst_acquire(device_t dev, const void *data, size_t len) {
+ struct cycv_reset *reset = NULL;
+ uint32_t value;
+
+ if (len != sizeof value)
+ goto err_decode;
+
+ value = of_decode_int(data);
+ if (value < 0 || value >
+ (CYCV_RSTMGR_MISCMODRST - CYCV_RSTMGR_PERMODRST + 4) / 4 * 32)
+ goto err_decode;
+
+ reset = kmem_alloc(sizeof *reset, KM_SLEEP);
+ reset->address = CYCV_RSTMGR_PERMODRST + value / 32 * 4;
+ reset->mask = 1 << (value % 32);
+
+ if (0) {
+err_decode:
+ aprint_debug_dev(dev, "couln't decode reset\n");
+ }
+ return reset;
+}
+
+static void
+cycv_rst_release(device_t dev, void *r) {
+ kmem_free(r, sizeof (struct cycv_reset));
+}
+
+static void
+cycv_rst_reset_set(device_t dev, struct cycv_reset *reset, int set) {
+ struct cycv_rstmgr_softc *sc = device_private(dev);
+ uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, reset->address);
+
+ if (set)
+ val |= reset->mask;
+ else
+ val &= ~reset->mask;
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, reset->address, val);
+}
+
+static int
+cycv_rst_reset_assert(device_t dev, void *r) {
+
+ cycv_rst_reset_set(dev, r, 1);
+
+ return 0;
+}
+
+static int
+cycv_rst_reset_deassert(device_t dev, void *r) {
+
+ cycv_rst_reset_set(dev, r, 0);
+
+ return 0;
+}
Index: src/sys/arch/arm/altera/cycv_var.h
diff -u /dev/null src/sys/arch/arm/altera/cycv_var.h:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/cycv_var.h Wed Sep 19 17:31:38 2018
@@ -0,0 +1,18 @@
+/* $NetBSD: cycv_var.h,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+#ifndef _ARM_ALTERA_CYCV_VAR_H
+#define _ARM_ALTERA_CYCV_VAR_H
+
+#include <sys/types.h>
+#include <sys/bus.h>
+
+extern struct bus_space armv7_generic_bs_tag;
+extern struct bus_space armv7_generic_a4x_bs_tag;
+extern struct arm32_bus_dma_tag arm_generic_dma_tag;
+
+void cycv_bootstrap(void);
+void cycv_cpuinit(void);
+
+uint32_t cycv_clkmgr_early_get_mpu_clk(void);
+uint32_t cycv_clkmgr_early_get_l4_sp_clk(void);
+
+#endif /* _ARM_ALTERA_CYCV_VAR_H */
Index: src/sys/arch/arm/altera/files.altera
diff -u /dev/null src/sys/arch/arm/altera/files.altera:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/altera/files.altera Wed Sep 19 17:31:38 2018
@@ -0,0 +1,37 @@
+# $NetBSD: files.altera,v 1.1 2018/09/19 17:31:38 aymeric Exp $
+#
+# Configuration for Altera SoC
+#
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/arm32/armv7_generic_space.c
+file arch/arm/arm/arm_generic_dma.c
+file arch/arm/arm/bus_space_a4x.S
+
+file arch/arm/altera/cycv_platform.c
+
+device cycvfdt : bus_space_generic, fdtbus
+attach cycvfdt at mainbus with cycv_fdt
+file arch/arm/altera/cycv_fdt.c cycv_fdt
+
+# Clock manager
+device cycvclkmgr : fdtbus
+attach cycvclkmgr at fdt
+file arch/arm/altera/cycv_clkmgr.c cycvclkmgr
+
+# Reset manager
+device cycvrstmgr : fdtbus
+attach cycvrstmgr at fdt
+file arch/arm/altera/cycv_rstmgr.c cycvrstmgr
+
+# GMAC
+attach awge at fdt with cycv_gmac
+file arch/arm/altera/cycv_gmac.c cycv_gmac
+
+# SD/MMC Host Controller
+attach dwcmmc at fdt with cycv_dwcmmc
+file arch/arm/altera/cycv_dwcmmc.c cycv_dwcmmc
Index: src/sys/arch/arm/dts/socfpga_cyclone5_de0_sockit.dts
diff -u /dev/null src/sys/arch/arm/dts/socfpga_cyclone5_de0_sockit.dts:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/arm/dts/socfpga_cyclone5_de0_sockit.dts Wed Sep 19 17:31:38 2018
@@ -0,0 +1,17 @@
+
+
+#include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts"
+
+/ {
+ soc {
+ gtimer@fffec200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffec200 0x20>;
+ clocks = <&mpu_periph_clk>;
+ interrupts = <1 11 0x301>;
+ };
+ usb@ffb40000 {
+ dr_mode = "host";
+ };
+ };
+};
Index: src/sys/arch/evbarm/altera/altera_start.S
diff -u /dev/null src/sys/arch/evbarm/altera/altera_start.S:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/altera/altera_start.S Wed Sep 19 17:31:38 2018
@@ -0,0 +1,126 @@
+/* $NetBSD: altera_start.S,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+#include "opt_arm_debug.h"
+#include "opt_fdt.h"
+
+#include <arm/armreg.h>
+#include <arm/asm.h>
+
+#include <arm/altera/cycv_reg.h>
+#include <evbarm/altera/platform.h>
+
+#include "assym.h"
+
+RCSID("$NetBSD: altera_start.S,v 1.1 2018/09/19 17:31:38 aymeric Exp $")
+
+#define MD_CPU_HATCH _C_LABEL(arm_fdt_cpu_hatch)
+
+#define INIT_MEMSIZE 128
+
+#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + \
+ INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
+
+#ifdef VERBOSE_INIT_ARM
+
+#ifndef CONADDR
+#define CONADDR 0xFFC02000
+#endif
+#define COM_MULT 4
+#ifdef __ARMEB__
+#define COM_BSWAP
+#endif
+
+#define XPUTC_COM
+#define XPUTC(x) mov r0, x; bl xputc
+#else
+#define XPUTC(x)
+
+#endif /* VERBOSE_INIT_ARM */
+
+ .section .start, "ax", %progbits
+
+ .global _C_LABEL(nanosoc_start)
+_C_LABEL(nanosoc_start):
+#ifdef __ARMEB__
+ setend be
+#endif
+
+ mov r9, #KERNEL_BASE_VOFFSET
+
+ cpsid if, #PSR_SVC32_MODE
+
+ movw r4, #:lower16:uboot_args
+ movt r4, #:upper16:uboot_args
+ sub r4, r4, r9
+ stmia r4, {r0-r3}
+
+#ifdef FDT
+ /*
+ * ARM boot protocol has FDT address in r2
+ */
+ movw r4, #:lower16:fdt_addr_r
+ movt r4, #:upper16:fdt_addr_r
+ sub r4, r4, r9
+ str r2, [r4]
+#endif
+
+ bl cortex_init
+
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+ movw r1, #:lower16:.Lmmu_init_table
+ movt r1, #:upper16:.Lmmu_init_table
+ bl arm_boot_l1pt_init
+
+ XPUTC(#'D')
+
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+#ifdef KERNEL_BASES_EQUAL
+ bl arm_cpuinit
+#else
+#ifdef VERBOSE_INIT_ARM
+ adr r11, xputc
+#endif
+ movw lr, #:lower16:1f
+ movt lr, #:upper16:1f
+ b arm_cpuinit
+ .pushsection .start, "ax", %progbits
+1:
+#endif
+/*
+ XPUTC2(#'Z')
+*/
+
+ b start
+ /* NOTREACHED */
+
+#ifdef KERNEL_BASES_EQUAL
+ .popsection
+#endif
+
+#include <arm/cortex/a9_mpsubr.S>
+
+.Lmmu_init_table:
+ /* Map reset vector to bootstrap secondary cpu */
+ MMU_INIT(0, 0, 1, L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+
+ MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+
+#if KERNEL_BASE_VOFFSET != 0
+ /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
+ MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
+ KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+#endif
+
+ /* Map peripherals */
+ MMU_INIT(CYCV_PERIPHERAL_VBASE, CYCV_PERIPHERAL_BASE,
+ (CYCV_PERIPHERAL_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* end of table */
+ MMU_INIT(0, 0, 0, 0)
+
+END(_C_LABEL(nanosoc_start))
Index: src/sys/arch/evbarm/altera/genassym.cf
diff -u /dev/null src/sys/arch/evbarm/altera/genassym.cf:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/altera/genassym.cf Wed Sep 19 17:31:38 2018
@@ -0,0 +1,7 @@
+include <dev/ic/ns16550reg.h>
+include <dev/ic/comreg.h>
+
+define LSR_TSRE LSR_TSRE
+define LSR_TXRDY LSR_TXRDY
+define COM_DATA com_data
+define COM_LSR com_lsr
Index: src/sys/arch/evbarm/altera/platform.h
diff -u /dev/null src/sys/arch/evbarm/altera/platform.h:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/altera/platform.h Wed Sep 19 17:31:38 2018
@@ -0,0 +1,4 @@
+/* $NetBSD: platform.h,v 1.1 2018/09/19 17:31:38 aymeric Exp $ */
+
+#define KERNEL_VM_BASE 0x80000000
+#define KERNEL_VM_SIZE 0x40000000
Index: src/sys/arch/evbarm/conf/NANOSOC
diff -u /dev/null src/sys/arch/evbarm/conf/NANOSOC:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/conf/NANOSOC Wed Sep 19 17:31:39 2018
@@ -0,0 +1,65 @@
+#
+# $NetBSD: NANOSOC,v 1.1 2018/09/19 17:31:39 aymeric Exp $
+#
+# Altera DE0 Nano SoC
+#
+
+include "arch/evbarm/conf/std.altera"
+include "arch/evbarm/conf/GENERIC.common"
+
+makeoptions DTSGNUARCH="arm"
+makeoptions DTSSUBDIR="socfpga"
+makeoptions DTS="socfpga_cyclone5_de0_sockit.dts"
+
+options CPU_CORTEXA9
+options MULTIPROCESSOR
+#options MEMSIZE=1024
+
+#options DEBUG
+#options LOCKDEBUG
+#options PMAP_DEBUG # Enable pmap_debug_level code
+#options IPKDB # remote kernel debugging
+#options VERBOSE_INIT_ARM # verbose bootstraping messages
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1
+
+config netbsd root on ? type ?
+
+armfdt0 at root
+simplebus* at fdt? pass 0
+
+cpus* at fdt? pass 0
+cpu* at fdt? pass 0
+
+cycvrstmgr0 at fdt? pass 0
+
+gic0 at fdt? pass 1
+armgic0 at gic?
+
+cycvclkmgr0 at fdt? pass 1
+
+a9tmr0 at fdt? pass 2
+arma9tmr0 at a9tmr0
+
+l2cc0 at fdt? pass 2
+arml2cc0 at l2cc0
+
+com* at fdt?
+options CONSADDR=0xFFC02000, CONSPEED=115200
+
+awge* at fdt?
+#micphy* at mii? phy?
+ukphy* at mii? phy?
+
+dwcmmc* at fdt?
+sdmmc* at dwcmmc?
+ld* at sdmmc?
+
+dwctwo* at fdt?
+usb* at dwctwo?
+
+include "dev/usb/usbdevices.config"
+
+no umidi
+
+cinclude "arch/evbarm/conf/NANOSOC.local"
Index: src/sys/arch/evbarm/conf/files.altera
diff -u /dev/null src/sys/arch/evbarm/conf/files.altera:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/conf/files.altera Wed Sep 19 17:31:39 2018
@@ -0,0 +1,9 @@
+# $NetBSD: files.altera,v 1.1 2018/09/19 17:31:39 aymeric Exp $
+#
+# Altera SoC configuration
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+include "arch/evbarm/conf/files.fdt"
+include "arch/arm/altera/files.altera"
Index: src/sys/arch/evbarm/conf/mk.altera
diff -u /dev/null src/sys/arch/evbarm/conf/mk.altera:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/conf/mk.altera Wed Sep 19 17:31:39 2018
@@ -0,0 +1,30 @@
+# $NetBSD: mk.altera,v 1.1 2018/09/19 17:31:39 aymeric Exp $
+CPPFLAGS+= -mcpu=cortex-a9 -mfpu=neon
+
+SYSTEM_FIRST_OBJ= altera_start.o
+SYSTEM_FIRST_SFILE= ${THISARM}/altera/altera_start.S
+
+GENASSYM_EXTRAS+= ${THISARM}/altera/genassym.cf
+
+_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
+
+MKUBOOTIMAGEARGS= -A arm -T kernel -O linux
+MKUBOOTIMAGEARGS+= -a $(KERNEL_BASE_PHYS) -e $(KERNEL_BASE_PHYS)
+MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
+MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
+MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
+
+SYSTEM_LD_TAIL_EXTRA+=; \
+ echo ${OBJCOPY} -S -O binary $@ $@.bin; \
+ ${OBJCOPY} -S -O binary $@ $@.bin; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} $@.bin $@.ub; \
+ echo ${TOOL_GZIP} -c $@.bin > $@.bin.gz; \
+ ${TOOL_GZIP} -c $@.bin > $@.bin.gz; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} $@.bin.gz $@.gz.ub
+
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}
Index: src/sys/arch/evbarm/conf/std.altera
diff -u /dev/null src/sys/arch/evbarm/conf/std.altera:1.1
--- /dev/null Wed Sep 19 17:31:39 2018
+++ src/sys/arch/evbarm/conf/std.altera Wed Sep 19 17:31:39 2018
@@ -0,0 +1,28 @@
+# $NetBSD: std.altera,v 1.1 2018/09/19 17:31:39 aymeric Exp $
+
+machine evbarm arm
+
+include "arch/evbarm/conf/std.evbarm"
+include "arch/evbarm/conf/files.altera"
+
+options FDT
+options DRAM_BLOCKS=256
+options FPU_VFP
+options TPIDRPRW_IS_CURCPU
+options ARM_HAS_VBAR
+options ARM_GENERIC_TODR
+options ARM_INTR_IMPL="<arch/arm/fdt/fdt_intr.h>"
+options __HAVE_FAST_SOFTINTS
+options __HAVE_CPU_COUNTER
+options __HAVE_CPU_UAREA_ALLOC_IDLELWP
+options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+options __BUS_SPACE_HAS_STREAM_METHODS
+
+options KERNEL_BASE_EXT=0x80000000
+
+makeoptions KERNEL_BASE_PHYS="0x10000"
+makeoptions KERNEL_BASE_VIRT="0x80010000"
+
+makeoptions BOARDTYPE="nanosoc"
+makeoptions BOARDMKFRAG="${THISARM}/conf/mk.altera"
+
