Module Name: src
Committed By: snj
Date: Tue Oct 9 15:43:38 UTC 2018
Modified Files:
src/sys/arch/x86/include [netbsd-7]: cacheinfo.h cpu.h specialreg.h
src/sys/arch/x86/x86 [netbsd-7]: cpu_topology.c identcpu.c
src/usr.sbin/cpuctl/arch [netbsd-7]: i386.c
Log Message:
Pull up following revision(s) (requested by msaitoh in ticket #1636):
sys/arch/x86/include/cacheinfo.h: 1.23-1.26
sys/arch/x86/include/cpu.h: 1.70
sys/arch/x86/include/specialreg.h:
1.91-1.93,1.98,1.100,1.102-1.124,1.126,1.130 via patch
sys/arch/x86/x86/cpu_topology.c: 1.10
sys/arch/x86/x86/identcpu.c: 1.56-1.57,1.70 via patch
usr.sbin/cpuctl/arch/i386.c: 1.71,1.75-1.79,1.81-1.85 via patch
Add some register definitions for x86:
- Add CLWB bit.
- Fix a few (unused) MSR values, and add some bit definitions of
MSR_EFER from Murray Armfield in PR#42861.
- CPUID_CFLUSH bit is not for CFLUSH insn but CLFLUSH insn, so modify
comments and snprintb() string.
- Define CPUID Fn00000001 %ebx bits and use them.
No functional change.
- Add Structured Extended Flags Enumeration Leaf's bit definitions:
AVX512_{IFMA,VBMI2,VNNI,BITALG,VPOPCNTDQ,4VNNIW,4FMAPS},GFNI&VAES.
- Add Turbo Boost Max Technology 3.0 bit.
- Add AMD SVM features definitions.
- Add Intel cpuid 7 %edx IBRS and STIBP bit definitions.
- Fix swapped comments for EFER LME and LMA
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add MSR_IA32_ARCH_CAPABILITIES definition.
- Add IA32_SPEC_CTRL MSR and IA32_PRED_CMD MSR.
- Add Intel Deterministic Address Translation Parameter Leaf(0x18)
definitions.
- s/CLFUSH/CLFLUSH/
- Add AMD's Disable Indirect Branch Predictor bit definition.
- Add the MSR bits definitions for IBRS, STIBP and IBPB.
- Add Intel Fn0000_0006 %eax new bit 14-20 (HWP stuff).
- Intel Fn0000_0007 %ecx bit 22 is for both RDPID and IA32_TSC_AUX.
- Add AMD's CPUID Fn80000001 %edx MMX and FXSR bit definitions.
- Add RDCL_NO and IBRS_ALL.
- Add SSBD and RSBA bit definitions.
- Add AMD's SSB bit definitions for F15H, F16H and F17H.
- Add cpuid 7 edx L1D_FLUSH bit.
- Add IA32_ARCH_SKIP_L1DFL_VMENTRY bit.
- Add IA32_FLUSH_CMD MSR.
- Add yet another Shared L2 TLB (2M/4M pages).
- Add 3way and 6way of L2 cache or TLB on AMD CPU.
- AMD L3 cache association bitfield is not 8bit but 4bit like others
association bitfields.
- Sort entries. No functional change.
- Modify comment, fix typo in comment and add comment.
cpuctl(8):
- Add detection for Quark X1000, Xeon E5 v4, E7 v4,
Core i7-69xx Extreme Edition, Xeon Scalable (Skylake),
Xeon Phi [357]200 (Knights Landing), Atom (Goldmont),
Atom (Denverton), Future Core (Cannon Lake), Atom (Goldmont Plus),
Xeon Phi 7215, 7285 and 7295 (Knights Mill) and
7th or 8th gen Core (Kaby Lake, Coffee Lake).
- Print Structured Extended Feature leaf Fn0000_0007 %ebx on AMD,too.
- Print Fn0000_0007 %ecx on Intel.
- Print Intel cpuid 7 %edx.
- Parse the TLB info from `cpuid leaf 18H' on Intel processor.
- Use aprint_error_dev() for error output.
To generate a diff of this commit:
cvs rdiff -u -r1.18.2.3 -r1.18.2.4 src/sys/arch/x86/include/cacheinfo.h
cvs rdiff -u -r1.66.4.1 -r1.66.4.2 src/sys/arch/x86/include/cpu.h
cvs rdiff -u -r1.78.4.5 -r1.78.4.6 src/sys/arch/x86/include/specialreg.h
cvs rdiff -u -r1.9 -r1.9.4.1 src/sys/arch/x86/x86/cpu_topology.c
cvs rdiff -u -r1.45.2.2 -r1.45.2.3 src/sys/arch/x86/x86/identcpu.c
cvs rdiff -u -r1.58.2.6 -r1.58.2.7 src/usr.sbin/cpuctl/arch/i386.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/cacheinfo.h
diff -u src/sys/arch/x86/include/cacheinfo.h:1.18.2.3 src/sys/arch/x86/include/cacheinfo.h:1.18.2.4
--- src/sys/arch/x86/include/cacheinfo.h:1.18.2.3 Thu Dec 8 00:15:25 2016
+++ src/sys/arch/x86/include/cacheinfo.h Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.18.2.3 2016/12/08 00:15:25 snj Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.18.2.4 2018/10/09 15:43:38 snj Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -35,9 +35,10 @@ struct x86_cache_info {
#define CAI_L2_DTLB2 15 /* L2 Data TLB (2/4M pages) */
#define CAI_L2_STLB 16 /* Shared L2 TLB (4K pages) */
#define CAI_L2_STLB2 17 /* Shared L2 TLB (4K/2M pages) */
-#define CAI_PREFETCH 18 /* Prefetch */
+#define CAI_L2_STLB3 18 /* Shared L2 TLB (2M/4M pages) */
+#define CAI_PREFETCH 19 /* Prefetch */
-#define CAI_COUNT 19
+#define CAI_COUNT 20
/*
* AMD Cache Info:
@@ -139,7 +140,7 @@ struct x86_cache_info {
/* L3 Cache */
#define AMD_L3_EDX_C_SIZE(x) ((((x) >> 18) & 0xffff) * 1024 * 512)
-#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xff)
+#define AMD_L3_EDX_C_ASSOC(x) (((x) >> 12) & 0xf)
#define AMD_L3_EDX_C_LPT(x) (((x) >> 8) & 0xf)
#define AMD_L3_EDX_C_LS(x) ( (x) & 0xff)
@@ -333,6 +334,7 @@ __CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1
__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \
__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \
+/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \
/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
__CI_TBL(0, 0, 0, 0, 0, NULL) \
}
@@ -340,7 +342,9 @@ __CI_TBL(0, 0, 0,
#define AMD_L2CACHE_INFO { \
__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
+__CI_TBL(0, 0x03, 3, 0, 0, NULL), \
__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
+__CI_TBL(0, 0x05, 6, 0, 0, NULL), \
__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
Index: src/sys/arch/x86/include/cpu.h
diff -u src/sys/arch/x86/include/cpu.h:1.66.4.1 src/sys/arch/x86/include/cpu.h:1.66.4.2
--- src/sys/arch/x86/include/cpu.h:1.66.4.1 Sun Mar 6 17:53:26 2016
+++ src/sys/arch/x86/include/cpu.h Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.66.4.1 2016/03/06 17:53:26 martin Exp $ */
+/* $NetBSD: cpu.h,v 1.66.4.2 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -170,7 +170,7 @@ struct cpu_info {
const struct cpu_functions *ci_func; /* start/stop functions */
struct trapframe *ci_ddb_regs;
- u_int ci_cflush_lsize; /* CFLUSH insn line size */
+ u_int ci_cflush_lsize; /* CLFLUSH insn line size */
struct x86_cache_info ci_cinfo[CAI_COUNT];
union descriptor *ci_gdt;
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.78.4.5 src/sys/arch/x86/include/specialreg.h:1.78.4.6
--- src/sys/arch/x86/include/specialreg.h:1.78.4.5 Thu Dec 8 00:15:25 2016
+++ src/sys/arch/x86/include/specialreg.h Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.78.4.5 2016/12/08 00:15:25 snj Exp $ */
+/* $NetBSD: specialreg.h,v 1.78.4.6 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -128,7 +128,7 @@
#define CPUID_DE 0x00000004 /* has debugging extension */
#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
#define CPUID_TSC 0x00000010 /* has time stamp counter */
-#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_MSR 0x00000020 /* has model specific registers */
#define CPUID_PAE 0x00000040 /* has phys address extension */
#define CPUID_MCE 0x00000080 /* has machine check exception */
#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
@@ -142,7 +142,7 @@
#define CPUID_PAT 0x00010000 /* Page Attribute Table */
#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_CFLUSH 0x00080000 /* CLFLUSH insn supported */
#define CPUID_B20 0x00100000 /* reserved */
#define CPUID_DS 0x00200000 /* Debug Store */
#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
@@ -161,7 +161,7 @@
"\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
"\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
"\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
- "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CFLUSH" \
+ "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFLUSH" \
"\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
"\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
"\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "SBF"
@@ -246,6 +246,12 @@
&& (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \
? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
+/* CPUID Fn00000001 %ebx */
+#define CPUID_BRAND_INDEX __BITS(7,0)
+#define CPUID_CLFLUSH_SIZE __BITS(15,8)
+#define CPUID_HTT_CORES __BITS(23,16)
+#define CPUID_LOCAL_APIC_ID __BITS(31,24)
+
/*
* Intel Deterministic Cache Parameter Leaf
* Fn0000_0004
@@ -290,13 +296,21 @@
#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
-#define CPUID_DSPM_HDC __BIT(13) /* HDC */
+#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
+#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
+#define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */
+#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */
+#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */
+#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */
+#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */
#define CPUID_DSPM_FLAGS "\20" \
"\1" "DTS" "\2" "IDA" "\3" "ARAT" \
"\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
"\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
- "\16" "HDC"
+ "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \
+ "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" \
+ "25" "HWP_IGNIDL"
/*
* Intel Digital Thermal Sensor and
@@ -313,38 +327,41 @@
* %eax: The Maximun input value for supported subleaf.
* %ebx: Feature bits.
* %ecx: Feature bits.
+ * %edx: Feature bits.
*/
/* %ebx */
-#define CPUID_SEF_FSGSBASE __BIT(0)
-#define CPUID_SEF_TSC_ADJUST __BIT(1)
-#define CPUID_SEF_SGX __BIT(2)
-#define CPUID_SEF_BMI1 __BIT(3)
-#define CPUID_SEF_HLE __BIT(4)
-#define CPUID_SEF_AVX2 __BIT(5)
-#define CPUID_SEF_FDPEXONLY __BIT(6)
-#define CPUID_SEF_SMEP __BIT(7)
-#define CPUID_SEF_BMI2 __BIT(8)
-#define CPUID_SEF_ERMS __BIT(9)
-#define CPUID_SEF_INVPCID __BIT(10)
-#define CPUID_SEF_RTM __BIT(11)
-#define CPUID_SEF_QM __BIT(12)
-#define CPUID_SEF_FPUCSDS __BIT(13)
-#define CPUID_SEF_MPX __BIT(14)
-#define CPUID_SEF_PQE __BIT(15)
-#define CPUID_SEF_AVX512F __BIT(16)
-#define CPUID_SEF_AVX512DQ __BIT(17)
-#define CPUID_SEF_RDSEED __BIT(18)
-#define CPUID_SEF_ADX __BIT(19)
-#define CPUID_SEF_SMAP __BIT(20)
-#define CPUID_SEF_CLFLUSHOPT __BIT(23)
-#define CPUID_SEF_PT __BIT(25)
-#define CPUID_SEF_AVX512PF __BIT(26)
-#define CPUID_SEF_AVX512ER __BIT(27)
-#define CPUID_SEF_AVX512CD __BIT(28)
-#define CPUID_SEF_SHA __BIT(29)
-#define CPUID_SEF_AVX512BW __BIT(30)
-#define CPUID_SEF_AVX512VL __BIT(31)
+#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
+#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
+#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extentions */
+#define CPUID_SEF_BMI1 __BIT(3) /* advanced bit manipulation ext. 1st grp */
+#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
+#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
+#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
+#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Excecution Prevention */
+#define CPUID_SEF_BMI2 __BIT(8) /* advanced bit manipulation ext. 2nd grp */
+#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
+#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
+#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
+#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
+#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
+#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
+#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
+#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
+#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
+#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
+#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
+#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
+#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
+#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
+#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
+#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
+#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
+#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
+#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
+#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
+#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
+#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
#define CPUID_SEF_FLAGS "\20" \
"\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
@@ -352,24 +369,48 @@
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
"\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" "\30" "CLFLUSHOPT" \
- "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
+ "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
+ "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
"\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
/* %ecx */
-#define CPUID_SEF_PREFETCHWT1 __BIT(0)
-#define CPUID_SEF_UMIP __BIT(2)
-#define CPUID_SEF_PKU __BIT(3)
-#define CPUID_SEF_OSPKE __BIT(4)
-#define CPUID_SEF_RDPID __BIT(22)
-#define CPUID_SEF_SGXLC __BIT(30)
+#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
+#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
+#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
+#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
+#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
+#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
+#define CPUID_SEF_GFNI __BIT(8)
+#define CPUID_SEF_VAES __BIT(9)
+#define CPUID_SEF_VPCLMULQDQ __BIT(10)
+#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector neural Network Instruction */
+#define CPUID_SEF_AVX512_BITALG __BIT(12)
+#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
+#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
+#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \
- "\5" "OSPKE" \
+ "\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU" \
+ "\5" "OSPKE" "\7" "AVX512_VBMI2" \
+ "\11" "GFNI" "\12" "VAES" "\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
+ "\15" "AVX512_BITALG" "\17" "AVX512_VPOPCNTDQ" \
"\27" "RDPID" \
"\37" "SGXLC"
+/* %edx */
+#define CPUID_SEF_AVX512_4VNNIW __BIT(2)
+#define CPUID_SEF_AVX512_4FMAPS __BIT(3)
+#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
+#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
+#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
+#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
+#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
+
+#define CPUID_SEF_FLAGS2 "\20" \
+ "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+ "\33" "IBRS" "\34" "STIBP" \
+ "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\40" "SSBD"
+
/*
* CPUID Processor extended state Enumeration Fn0000000d
*
@@ -401,6 +442,35 @@
#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
+/*
+ * Intel Deterministic Address Translation Parameter Leaf
+ * Fn0000_0018
+ */
+
+/* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */
+
+/* %ebx */
+#define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */
+#define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */
+#define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */
+#define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */
+#define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */
+#define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */
+#define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */
+
+/* Number of sets: %ecx */
+
+/* %edx */
+#define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */
+#define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */
+#define CPUID_DATP_TCTYPE_D 1 /* Data TLB */
+#define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */
+#define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */
+#define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */
+#define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */
+#define CPUID_DATP_SHAREING __BITS(25, 14) /* shareing */
+
+
/* Intel Fn80000001 extended features - %edx */
#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
@@ -422,11 +492,14 @@
"\06" "LZCNT" \
"\11" "PREFETCHW"
+
/* AMD/VIA Fn80000001 extended features - %edx */
/* CPUID_SYSCALL SYSCALL/SYSRET */
#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
#define CPUID_NOX 0x00100000 /* No Execute Page Protection */
#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
+/* CPUID_MMX MMX supported */
+/* CPUID_FXSR fast FP/MMX save/restore */
#define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */
/* CPUID_P1GB 1GB Large Page Support */
/* CPUID_RDTSCP Read TSC Pair Instruction */
@@ -435,8 +508,10 @@
#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
#define CPUID_EXT_FLAGS "\20" \
- "\14" "SYSCALL/SYSRET" "\24" "MPC" "\25" "NOX" \
- "\27" "MMXX" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \
+ "\14" "SYSCALL/SYSRET" \
+ "\24" "MPC" \
+ "\25" "NOX" "\27" "MMXX" "\30" "MMX" \
+ "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \
"\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW"
/* AMD Fn80000001 extended features - %ecx */
@@ -511,13 +586,18 @@
#define CPUID_AMD_SVM_FlushByASID 0x00000040
#define CPUID_AMD_SVM_DecodeAssist 0x00000080
#define CPUID_AMD_SVM_PauseFilter 0x00000400
+#define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */
+#define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */
+#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */
+#define CPUID_AMD_SVM_vGIF 0x00010000 /* Virtualized GIF */
#define CPUID_AMD_SVM_FLAGS "\20" \
- "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
- "\5" "TSCRate" "\6" "VMCBCleanBits" \
- "\7" "FlushByASID" "\10" "DecodeAssist" \
+ "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
+ "\5" "TSCRate" "\6" "VMCBCleanBits" \
+ "\7" "FlushByASID" "\10" "DecodeAssist" \
"\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
- "\15" "B12" "\16" "B13" "\17" "B17" "\20" "B18" \
- "\21" "B19"
+ "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
+ "\20" "V_VMSAVE_VMLOAD" \
+ "\21" "VGIF"
/*
* Centaur Extended Feature flags
@@ -551,6 +631,12 @@
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
#define MSR_TEST_CTL 0x033
+#define MSR_IA32_SPEC_CTRL 0x048
+#define IA32_SPEC_CTRL_IBRS 0x01
+#define IA32_SPEC_CTRL_STIBP 0x02
+#define IA32_SPEC_CTRL_SSBD 0x04
+#define MSR_IA32_PRED_CMD 0x049
+#define IA32_PRED_CMD_IBPB 0x01
#define MSR_BIOS_UPDT_TRIG 0x079
#define MSR_BBL_CR_D0 0x088 /* PII+ only */
#define MSR_BBL_CR_D1 0x089 /* PII+ only */
@@ -563,6 +649,14 @@
#define MSR_APERF 0x0e8
#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
#define MSR_MTRRcap 0x0fe
+#define MSR_IA32_ARCH_CAPABILITIES 0x10a
+#define IA32_ARCH_RDCL_NO 0x01
+#define IA32_ARCH_IBRS_ALL 0x02
+#define IA32_ARCH_RSBA 0x04
+#define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
+#define IA32_ARCH_SSB_NO 0x10
+#define MSR_IA32_FLUSH_CMD 0x10b
+#define IA32_FLUSH_CMD_L1D_FLUSH 0x01
#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
@@ -648,14 +742,14 @@
#define MSR_MC2_STATUS 0x409
#define MSR_MC2_ADDR 0x40a
#define MSR_MC2_MISC 0x40b
-#define MSR_MC4_CTL 0x40c
-#define MSR_MC4_STATUS 0x40d
-#define MSR_MC4_ADDR 0x40e
-#define MSR_MC4_MISC 0x40f
-#define MSR_MC3_CTL 0x410
-#define MSR_MC3_STATUS 0x411
-#define MSR_MC3_ADDR 0x412
-#define MSR_MC3_MISC 0x413
+#define MSR_MC3_CTL 0x40c
+#define MSR_MC3_STATUS 0x40d
+#define MSR_MC3_ADDR 0x40e
+#define MSR_MC3_MISC 0x40f
+#define MSR_MC4_CTL 0x410
+#define MSR_MC4_STATUS 0x411
+#define MSR_MC4_ADDR 0x412
+#define MSR_MC4_MISC 0x413
/* 0x480 - 0x490 VMX */
/*
@@ -691,13 +785,16 @@
/*
* AMD K8 (Opteron) MSRs.
*/
-#define MSR_SYSCFG 0xc0000010
+#define MSR_SYSCFG 0xc0010010
#define MSR_EFER 0xc0000080 /* Extended feature enable */
-#define EFER_SCE 0x00000001 /* SYSCALL extension */
-#define EFER_LME 0x00000100 /* Long Mode Active */
-#define EFER_LMA 0x00000400 /* Long Mode Enabled */
-#define EFER_NXE 0x00000800 /* No-Execute Enabled */
+#define EFER_SCE 0x00000001 /* SYSCALL extension */
+#define EFER_LME 0x00000100 /* Long Mode Enable */
+#define EFER_LMA 0x00000400 /* Long Mode Active */
+#define EFER_NXE 0x00000800 /* No-Execute Enabled */
+#define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */
+#define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */
+#define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */
#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
@@ -730,9 +827,13 @@
#define MSR_LS_CFG 0xc0011020
#define LS_CFG_DIS_LS2_SQUISH 0x02000000
+#define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL
+#define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL
+#define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL
#define MSR_IC_CFG 0xc0011021
#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
+#define IC_CFG_DIS_IND 0x00004000
#define MSR_DC_CFG 0xc0011022
#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
Index: src/sys/arch/x86/x86/cpu_topology.c
diff -u src/sys/arch/x86/x86/cpu_topology.c:1.9 src/sys/arch/x86/x86/cpu_topology.c:1.9.4.1
--- src/sys/arch/x86/x86/cpu_topology.c:1.9 Sat Feb 22 17:48:08 2014
+++ src/sys/arch/x86/x86/cpu_topology.c Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $ */
+/* $NetBSD: cpu_topology.c,v 1.9.4.1 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 2009 Mindaugas Rasiukevicius <rmind at NetBSD org>,
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.9 2014/02/22 17:48:08 dsl Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_topology.c,v 1.9.4.1 2018/10/09 15:43:38 snj Exp $");
#include <sys/param.h>
#include <sys/bitops.h>
@@ -81,7 +81,7 @@ x86_cpu_topology(struct cpu_info *ci)
if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
/* Maximum number of LPs sharing a cache (ebx[23:16]). */
x86_cpuid(1, descs);
- lp_max = (descs[1] >> 16) & 0xff;
+ lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
} else {
lp_max = 1;
}
Index: src/sys/arch/x86/x86/identcpu.c
diff -u src/sys/arch/x86/x86/identcpu.c:1.45.2.2 src/sys/arch/x86/x86/identcpu.c:1.45.2.3
--- src/sys/arch/x86/x86/identcpu.c:1.45.2.2 Sun Mar 6 17:53:26 2016
+++ src/sys/arch/x86/x86/identcpu.c Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.45.2.2 2016/03/06 17:53:26 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.45.2.3 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.45.2.2 2016/03/06 17:53:26 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.45.2.3 2018/10/09 15:43:38 snj Exp $");
#include "opt_xen.h"
@@ -824,8 +824,9 @@ cpu_probe(struct cpu_info *ci)
/* CLFLUSH line size is next 8 bits */
if (ci->ci_feat_val[0] & CPUID_CFLUSH)
- ci->ci_cflush_lsize = ((miscbytes >> 8) & 0xff) << 3;
- ci->ci_initapicid = (miscbytes >> 24) & 0xff;
+ ci->ci_cflush_lsize
+ = __SHIFTOUT(miscbytes, CPUID_CLFLUSH_SIZE) << 3;
+ ci->ci_initapicid = __SHIFTOUT(miscbytes, CPUID_LOCAL_APIC_ID);
}
/*
Index: src/usr.sbin/cpuctl/arch/i386.c
diff -u src/usr.sbin/cpuctl/arch/i386.c:1.58.2.6 src/usr.sbin/cpuctl/arch/i386.c:1.58.2.7
--- src/usr.sbin/cpuctl/arch/i386.c:1.58.2.6 Thu Dec 8 00:15:25 2016
+++ src/usr.sbin/cpuctl/arch/i386.c Tue Oct 9 15:43:38 2018
@@ -1,4 +1,4 @@
-/* $NetBSD: i386.c,v 1.58.2.6 2016/12/08 00:15:25 snj Exp $ */
+/* $NetBSD: i386.c,v 1.58.2.7 2018/10/09 15:43:38 snj Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
#include <sys/cdefs.h>
#ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.58.2.6 2016/12/08 00:15:25 snj Exp $");
+__RCSID("$NetBSD: i386.c,v 1.58.2.7 2018/10/09 15:43:38 snj Exp $");
#endif /* not lint */
#include <sys/types.h>
@@ -92,20 +92,22 @@ __RCSID("$NetBSD: i386.c,v 1.58.2.6 2016
struct cpu_info {
const char *ci_dev;
- int32_t ci_cpu_type; /* for cpu's without cpuid */
+ int32_t ci_cpu_type; /* for cpu's without cpuid */
int32_t ci_cpuid_level; /* highest cpuid supported */
uint32_t ci_cpuid_extlevel; /* highest cpuid extended func lv */
uint32_t ci_signature; /* X86 cpuid type */
uint32_t ci_family; /* from ci_signature */
uint32_t ci_model; /* from ci_signature */
- uint32_t ci_feat_val[8]; /* X86 CPUID feature bits
+ uint32_t ci_feat_val[9]; /* X86 CPUID feature bits
* [0] basic features %edx
* [1] basic features %ecx
* [2] extended features %edx
* [3] extended features %ecx
* [4] VIA padlock features
- * [5] XCR0 bits (d:0 %eax)
- * [6] xsave flags (d:1 %eax)
+ * [5] structure ext. feat. %ebx
+ * [6] structure ext. feat. %ecx
+ * [7] XCR0 bits (d:0 %eax)
+ * [8] xsave flags (d:1 %eax)
*/
uint32_t ci_cpu_class; /* CPU class */
uint32_t ci_brand_id; /* Intel brand id */
@@ -159,11 +161,11 @@ static const struct x86_cache_info intel
static const char * const i386_intel_brand[] = {
"", /* Unsupported */
"Celeron", /* Intel (R) Celeron (TM) processor */
- "Pentium III", /* Intel (R) Pentium (R) III processor */
+ "Pentium III", /* Intel (R) Pentium (R) III processor */
"Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */
- "Pentium III", /* Intel (R) Pentium (R) III processor */
+ "Pentium III", /* Intel (R) Pentium (R) III processor */
"", /* 0x05: Reserved */
- "Mobile Pentium III", /* Mobile Intel (R) Pentium (R) III processor-M */
+ "Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
"Pentium 4", /* Intel (R) Pentium (R) 4 processor */
@@ -175,11 +177,11 @@ static const char * const i386_intel_bra
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
"", /* 0x10: Reserved */
"Mobile Genuine", /* Moblie Genuine Intel (R) processor */
- "Celeron M", /* Intel (R) Celeron (R) M processor */
+ "Celeron M", /* Intel (R) Celeron (R) M processor */
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
- "Celeron", /* Intel (R) Celeron (R) processor */
+ "Celeron", /* Intel (R) Celeron (R) processor */
"Mobile Genuine", /* Moblie Genuine Intel (R) processor */
- "Pentium M", /* Intel (R) Pentium (R) M processor */
+ "Pentium M", /* Intel (R) Pentium (R) M processor */
"Mobile Celeron", /* Mobile Intel (R) Celeron (R) processor */
};
@@ -213,8 +215,8 @@ static void powernow_probe(struct cpu_in
static void intel_family_new_probe(struct cpu_info *);
static void via_cpu_probe(struct cpu_info *);
/* (Cache) Info functions */
-static void intel_cpu_cacheinfo(struct cpu_info *);
-static void amd_cpu_cacheinfo(struct cpu_info *);
+static void intel_cpu_cacheinfo(struct cpu_info *);
+static void amd_cpu_cacheinfo(struct cpu_info *);
static void via_cpu_cacheinfo(struct cpu_info *);
static void tmx86_get_longrun_status(u_int *, u_int *, u_int *);
static void transmeta_cpu_info(struct cpu_info *);
@@ -249,7 +251,7 @@ const struct cpu_nocpuid_nameclass i386_
NULL, NULL, NULL }, /* CPU_486DLC */
{ CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486,
NULL, NULL, NULL }, /* CPU_6x86 */
- { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386,
+ { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386,
NULL, NULL, NULL }, /* CPU_NX586 */
};
@@ -369,17 +371,19 @@ const struct cpu_cpuid_nameclass i386_cp
[0x4d] = "Atom C2000",
[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
- [0x55] = "Future Xeon",
+ [0x55] = "Xeon Scalable (Skylake)",
[0x56] = "Xeon D-1500 (Broadwell)",
- [0x57] = "Xeon Phi [357]200",
+ [0x57] = "Xeon Phi [357]200 (Knights Landing)",
[0x5a] = "Atom E3500",
- [0x5c] = "Next Atom (Goldmont)",
+ [0x5c] = "Atom (Goldmont)",
[0x5d] = "Atom X3-C3000 (Silvermont)",
[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
- [0x5f] = "Future Atom (Denverton)",
- [0x85] = "Future Xeon Phi",
- [0x8e] = "7th gen Core (Kaby Lake)",
- [0x9e] = "7th gen Core (Kaby Lake)",
+ [0x5f] = "Atom (Goldmont, Denverton)",
+ [0x66] = "Future Core (Cannon Lake)",
+ [0x7a] = "Atom (Goldmont Plus)",
+ [0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
+ [0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
+ [0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake)",
},
"Pentium Pro, II or III", /* Default */
NULL,
@@ -1021,8 +1025,10 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
desc);
if (cai != NULL)
ci->ci_cinfo[cai->cai_index] = *cai;
- else if ((verbose != 0) && (desc != 0xff))
- printf("Unknown cacheinfo desc %02x\n",
+ else if ((verbose != 0) && (desc != 0xff)
+ && (desc != 0xfe))
+ aprint_error_dev(ci->ci_dev, "error:"
+ " Unknown cacheinfo desc %02x\n",
desc);
}
}
@@ -1065,7 +1071,8 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
break;
}
if (caitype == -1) {
- printf("unknown cache level&type (%d & %d)\n",
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown cache level&type (%d & %d)\n",
level, type);
continue;
}
@@ -1080,6 +1087,140 @@ intel_cpu_cacheinfo(struct cpu_info *ci)
ci->ci_cinfo[caitype].cai_associativity = ways;
ci->ci_cinfo[caitype].cai_linesize = linesize;
}
+
+ if (ci->ci_cpuid_level < 0x18)
+ return;
+ /* Parse the TLB info from `cpuid leaf 18H', if we have it. */
+ x86_cpuid(0x18, descs);
+ iterations = descs[0];
+ for (i = 0; i <= iterations; i++) {
+ uint32_t pgsize;
+ bool full;
+
+ x86_cpuid2(0x18, i, descs);
+ type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE);
+ if (type == CPUID_DATP_TCTYPE_N)
+ continue;
+ level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL);
+ pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DATP_TCTYPE_I) {
+ switch (pgsize) {
+ case CPUID_DATP_PGSIZE_4KB:
+ caitype = CAI_ITLB;
+ break;
+ case CPUID_DATP_PGSIZE_2MB
+ | CPUID_DATP_PGSIZE_4MB:
+ caitype = CAI_ITLB2;
+ break;
+ case CPUID_DATP_PGSIZE_1GB:
+ caitype = CAI_L1_1GBITLB;
+ break;
+ default:
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown ITLB size (%d)\n",
+ pgsize);
+ caitype = CAI_ITLB;
+ break;
+ }
+ } else if (type == CPUID_DATP_TCTYPE_D) {
+ switch (pgsize) {
+ case CPUID_DATP_PGSIZE_4KB:
+ caitype = CAI_DTLB;
+ break;
+ case CPUID_DATP_PGSIZE_2MB
+ | CPUID_DATP_PGSIZE_4MB:
+ caitype = CAI_DTLB2;
+ break;
+ case CPUID_DATP_PGSIZE_1GB:
+ caitype = CAI_L1_1GBDTLB;
+ break;
+ default:
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown DTLB size (%d)\n",
+ pgsize);
+ caitype = CAI_DTLB;
+ break;
+ }
+ } else
+ caitype = -1;
+ break;
+ case 2:
+ if (type == CPUID_DATP_TCTYPE_I)
+ caitype = CAI_L2_ITLB;
+ else if (type == CPUID_DATP_TCTYPE_D)
+ caitype = CAI_L2_DTLB;
+ else if (type == CPUID_DATP_TCTYPE_U) {
+ switch (pgsize) {
+ case CPUID_DATP_PGSIZE_4KB:
+ caitype = CAI_L2_STLB;
+ break;
+ case CPUID_DATP_PGSIZE_4KB
+ | CPUID_DATP_PGSIZE_2MB:
+ caitype = CAI_L2_STLB2;
+ break;
+ case CPUID_DATP_PGSIZE_2MB
+ | CPUID_DATP_PGSIZE_4MB:
+ caitype = CAI_L2_STLB3;
+ break;
+ default:
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown L2 STLB size (%d)\n",
+ pgsize);
+ caitype = CAI_DTLB;
+ break;
+ }
+ } else
+ caitype = -1;
+ break;
+ case 3:
+ /* XXX need work for L3 TLB */
+ caitype = CAI_L3CACHE;
+ break;
+ default:
+ caitype = -1;
+ break;
+ }
+ if (caitype == -1) {
+ aprint_error_dev(ci->ci_dev,
+ "error: unknown TLB level&type (%d & %d)\n",
+ level, type);
+ continue;
+ }
+ switch (pgsize) {
+ case CPUID_DATP_PGSIZE_4KB:
+ linesize = 4 * 1024;
+ break;
+ case CPUID_DATP_PGSIZE_2MB:
+ linesize = 2 * 1024 * 1024;
+ break;
+ case CPUID_DATP_PGSIZE_4MB:
+ linesize = 4 * 1024 * 1024;
+ break;
+ case CPUID_DATP_PGSIZE_1GB:
+ linesize = 1024 * 1024 * 1024;
+ break;
+ case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB:
+ aprint_error_dev(ci->ci_dev,
+ "WARINING: Currently 2M/4M info can't print correctly\n");
+ linesize = 4 * 1024 * 1024;
+ break;
+ default:
+ aprint_error_dev(ci->ci_dev,
+ "error: Unknown size combination\n");
+ linesize = 4 * 1024;
+ break;
+ }
+ ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
+ sets = descs[2];
+ full = descs[3] & CPUID_DATP_FULLASSOC;
+ ci->ci_cinfo[caitype].cai_totalsize
+ = ways * sets; /* entries */
+ ci->ci_cinfo[caitype].cai_associativity
+ = full ? 0xff : ways;
+ ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */
+ }
}
static const struct x86_cache_info amd_cpuid_l2cache_assoc_info[] =
@@ -1504,9 +1645,9 @@ cpu_probe_base_features(struct cpu_info
ci->ci_model = CPUID_TO_MODEL(ci->ci_signature);
/* Brand is low order 8 bits of ebx */
- ci->ci_brand_id = descs[1] & 0xff;
+ ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX);
/* Initial local APIC ID */
- ci->ci_initapicid = (descs[1] >> 24) & 0xff;
+ ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID);
ci->ci_feat_val[1] = descs[2];
ci->ci_feat_val[0] = descs[3];
@@ -1525,18 +1666,25 @@ cpu_probe_base_features(struct cpu_info
ci->ci_cpu_serial[1] = descs[3];
}
+ if (ci->ci_cpuid_level < 0x7)
+ return;
+
+ x86_cpuid(7, descs);
+ ci->ci_feat_val[5] = descs[1];
+ ci->ci_feat_val[6] = descs[2];
+
if (ci->ci_cpuid_level < 0xd)
return;
/* Get support XCR0 bits */
x86_cpuid2(0xd, 0, descs);
- ci->ci_feat_val[5] = descs[0]; /* Actually 64 bits */
+ ci->ci_feat_val[7] = descs[0]; /* Actually 64 bits */
ci->ci_cur_xsave = descs[1];
ci->ci_max_xsave = descs[2];
/* Additional flags (eg xsaveopt support) */
x86_cpuid2(0xd, 1, descs);
- ci->ci_feat_val[6] = descs[0]; /* Actually 64 bits */
+ ci->ci_feat_val[8] = descs[0]; /* Actually 64 bits */
}
static void
@@ -1659,7 +1807,7 @@ identifycpu_cpuids(struct cpu_info *ci)
if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
x86_cpuid(1, descs);
- lp_max = (descs[1] >> 16) & 0xff;
+ lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
}
if (ci->ci_cpuid_level >= 4) {
x86_cpuid2(4, 0, descs);
@@ -1780,7 +1928,7 @@ identifycpu(int fd, const char *cpuname)
cpufam = &cpup->cpu_family[family - CPU_MINFAMILY];
name = cpufam->cpu_models[ci->ci_model];
if (name == NULL || *name == '\0')
- name = cpufam->cpu_model_default;
+ name = cpufam->cpu_model_default;
class = cpufam->cpu_class;
ci->ci_info = cpufam->cpu_info;
@@ -1796,7 +1944,7 @@ identifycpu(int fd, const char *cpuname)
__arraycount(i386_intel_brand) &&
i386_intel_brand[ci->ci_brand_id])
name =
- i386_intel_brand[ci->ci_brand_id];
+ i386_intel_brand[ci->ci_brand_id];
}
if (cpu_vendor == CPUVENDOR_AMD) {
@@ -1883,14 +2031,25 @@ identifycpu(int fd, const char *cpuname)
print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK,
ci->ci_feat_val[4]);
+ if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
+ print_bits(cpuname, "features5", CPUID_SEF_FLAGS,
+ ci->ci_feat_val[5]);
+ if (cpu_vendor == CPUVENDOR_INTEL)
+ print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
+ ci->ci_feat_val[6]);
+
+ if ((cpu_vendor == CPUVENDOR_INTEL) && (ci->ci_cpuid_level >= 7)) {
+ x86_cpuid(7, descs);
+ print_bits(cpuname, "SEF edx", CPUID_SEF_FLAGS2, descs[3]);
+ }
- print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[5]);
+ print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[7]);
print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
- ci->ci_feat_val[6]);
+ ci->ci_feat_val[8]);
if (ci->ci_max_xsave != 0) {
aprint_normal("%s: xsave area size: current %d, maximum %d",
- cpuname, ci->ci_cur_xsave, ci->ci_max_xsave);
+ cpuname, ci->ci_cur_xsave, ci->ci_max_xsave);
aprint_normal(", xgetbv %sabled\n",
ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis");
if (ci->ci_feat_val[1] & CPUID2_OSXSAVE)
@@ -1908,9 +2067,8 @@ identifycpu(int fd, const char *cpuname)
ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536);
}
- if (ci->ci_cpu_class == CPUCLASS_386) {
+ if (ci->ci_cpu_class == CPUCLASS_386)
errx(1, "NetBSD requires an 80486 or later processor");
- }
if (ci->ci_cpu_type == CPU_486DLC) {
#ifndef CYRIX_CACHE_WORKS
@@ -1945,13 +2103,13 @@ identifycpu(int fd, const char *cpuname)
powernow_probe(ci);
if ((data[0] >= 0x8000000a)
- && (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
+ && (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
x86_cpuid(0x8000000a, data);
aprint_verbose("%s: SVM Rev. %d\n", cpuname,
data[0] & 0xf);
aprint_verbose("%s: SVM NASID %d\n", cpuname, data[1]);
- print_bits(cpuname, "SVM features", CPUID_AMD_SVM_FLAGS,
- data[3]);
+ print_bits(cpuname, "SVM features",
+ CPUID_AMD_SVM_FLAGS, data[3]);
}
} else if (cpu_vendor == CPUVENDOR_INTEL) {
uint32_t data[4];
@@ -1969,8 +2127,6 @@ identifycpu(int fd, const char *cpuname)
case 7:
aprint_verbose("%s: SEF highest subleaf %08x\n",
cpuname, data[0]);
- print_bits(cpuname, "SEF-main", CPUID_SEF_FLAGS,
- data[1]);
break;
#if 0
default:
@@ -2020,7 +2176,7 @@ identifycpu(int fd, const char *cpuname)
printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version);
else if (cpu_vendor == CPUVENDOR_INTEL)
printf("%s: microcode version 0x%x, platform ID %d\n", cpuname,
- ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
+ ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
}
static const struct x86_cache_info *
@@ -2057,14 +2213,14 @@ print_cache_config(struct cpu_info *ci,
aprint_verbose("%s ", cai->cai_string);
} else {
(void)humanize_number(human_num, sizeof(human_num),
- cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE);
+ cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE);
aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize);
}
switch (cai->cai_associativity) {
- case 0:
+ case 0:
aprint_verbose("disabled");
break;
- case 1:
+ case 1:
aprint_verbose("direct-mapped");
break;
case 0xff:
@@ -2098,7 +2254,7 @@ print_tlb_config(struct cpu_info *ci, in
aprint_verbose("%s", cai->cai_string);
} else {
(void)humanize_number(human_num, sizeof(human_num),
- cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE);
+ cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE);
aprint_verbose("%d %s entries ", cai->cai_totalsize,
human_num);
switch (cai->cai_associativity) {
@@ -2143,7 +2299,7 @@ x86_print_cache_and_tlb_info(struct cpu_
}
if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) {
aprint_verbose_dev(ci->ci_dev, "%dB prefetching",
- ci->ci_cinfo[CAI_PREFETCH].cai_linesize);
+ ci->ci_cinfo[CAI_PREFETCH].cai_linesize);
if (sep != NULL)
aprint_verbose("\n");
}
@@ -2174,6 +2330,7 @@ x86_print_cache_and_tlb_info(struct cpu_
if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL);
sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
+ sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
if (sep != NULL)
aprint_verbose("\n");
}
