Module Name: src Committed By: jmcneill Date: Sun Oct 21 00:42:06 UTC 2018
Modified Files: src/sys/arch/arm/acpi: acpi_pci_machdep.c gic_acpi.c src/sys/arch/arm/cortex: files.cortex src/sys/arch/arm/fdt: acpi_fdt.c src/sys/arch/arm/include: pci_machdep.h src/sys/arch/evbarm/conf: files.evbarm std.generic64 Added Files: src/sys/arch/arm/cortex: gic_v2m.c gic_v2m.h src/sys/arch/arm/pci: files.pci pci_msi_machdep.c pci_msi_machdep.h Log Message: Add support for PCI MSI using ARM GICv2m. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/acpi/acpi_pci_machdep.c cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/acpi/gic_acpi.c cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/cortex/files.cortex cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/cortex/gic_v2m.c \ src/sys/arch/arm/cortex/gic_v2m.h cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/fdt/acpi_fdt.c cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/include/pci_machdep.h cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/pci/files.pci \ src/sys/arch/arm/pci/pci_msi_machdep.c \ src/sys/arch/arm/pci/pci_msi_machdep.h cvs rdiff -u -r1.31 -r1.32 src/sys/arch/evbarm/conf/files.evbarm cvs rdiff -u -r1.7 -r1.8 src/sys/arch/evbarm/conf/std.generic64 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
Modified files: Index: src/sys/arch/arm/acpi/acpi_pci_machdep.c diff -u src/sys/arch/arm/acpi/acpi_pci_machdep.c:1.2 src/sys/arch/arm/acpi/acpi_pci_machdep.c:1.3 --- src/sys/arch/arm/acpi/acpi_pci_machdep.c:1.2 Fri Oct 19 11:40:27 2018 +++ src/sys/arch/arm/acpi/acpi_pci_machdep.c Sun Oct 21 00:42:05 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: acpi_pci_machdep.c,v 1.2 2018/10/19 11:40:27 jmcneill Exp $ */ +/* $NetBSD: acpi_pci_machdep.c,v 1.3 2018/10/21 00:42:05 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -30,7 +30,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.2 2018/10/19 11:40:27 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: acpi_pci_machdep.c,v 1.3 2018/10/21 00:42:05 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -57,8 +57,7 @@ __KERNEL_RCSID(0, "$NetBSD: acpi_pci_mac #include <arm/acpi/acpi_pci_machdep.h> -#define IH_INDEX_MASK 0x0000ffff -#define IH_MPSAFE 0x80000000 +#include <arm/pci/pci_msi_machdep.h> struct acpi_pci_prt { u_int prt_bus; @@ -331,7 +330,13 @@ done: static const char * acpi_pci_md_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) { - snprintf(buf, len, "irq %d", (int)(ih & IH_INDEX_MASK)); + const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); + + if (ih & ARM_PCI_INTR_MSI) + snprintf(buf, len, "irq %d (MSI)", irq); + else + snprintf(buf, len, "irq %d", irq); + return buf; } @@ -347,9 +352,9 @@ acpi_pci_md_intr_setattr(void *v, pci_in switch (attr) { case PCI_INTR_MPSAFE: if (data) - *ih |= IH_MPSAFE; + *ih |= ARM_PCI_INTR_MPSAFE; else - *ih &= ~IH_MPSAFE; + *ih &= ~ARM_PCI_INTR_MPSAFE; return 0; default: return ENODEV; @@ -360,8 +365,13 @@ static void * acpi_pci_md_intr_establish(void *v, pci_intr_handle_t ih, int ipl, int (*callback)(void *), void *arg) { - const int irq = ih & IH_INDEX_MASK; - const int mpsafe = (ih & IH_MPSAFE) ? IST_MPSAFE : 0; + struct acpi_pci_context * const ap = v; + + if (ih & ARM_PCI_INTR_MSI) + return arm_pci_msi_intr_establish(&ap->ap_pc, ih, ipl, callback, arg); + + const int irq = (int)__SHIFTOUT(ih, ARM_PCI_INTR_IRQ); + const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0; return intr_establish(irq, ipl, IST_LEVEL | mpsafe, callback, arg); } Index: src/sys/arch/arm/acpi/gic_acpi.c diff -u src/sys/arch/arm/acpi/gic_acpi.c:1.1 src/sys/arch/arm/acpi/gic_acpi.c:1.2 --- src/sys/arch/arm/acpi/gic_acpi.c:1.1 Fri Oct 12 22:20:04 2018 +++ src/sys/arch/arm/acpi/gic_acpi.c Sun Oct 21 00:42:05 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: gic_acpi.c,v 1.1 2018/10/12 22:20:04 jmcneill Exp $ */ +/* $NetBSD: gic_acpi.c,v 1.2 2018/10/21 00:42:05 jmcneill Exp $ */ /*- * Copyright (c) 2018 The NetBSD Foundation, Inc. @@ -30,30 +30,36 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.1 2018/10/12 22:20:04 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: gic_acpi.c,v 1.2 2018/10/21 00:42:05 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> #include <sys/cpu.h> #include <sys/device.h> +#include <sys/kmem.h> #include <dev/acpi/acpireg.h> #include <dev/acpi/acpivar.h> #include <arm/cortex/gic_intr.h> +#include <arm/cortex/gic_reg.h> +#include <arm/cortex/gic_v2m.h> #include <arm/cortex/mpcore_var.h> #include <dev/fdt/fdtvar.h> -#define GICD_SIZE 0x1000 -#define GICC_SIZE 0x1000 +#define GICD_SIZE 0x1000 +#define GICC_SIZE 0x1000 +#define GICMSIFRAME_SIZE 0x1000 extern struct bus_space arm_generic_bs_tag; +extern struct pic_softc *pic_list[]; static int gic_acpi_match(device_t, cfdata_t, void *); static void gic_acpi_attach(device_t, device_t, void *); static ACPI_STATUS gic_acpi_find_gicc(ACPI_SUBTABLE_HEADER *, void *); +static ACPI_STATUS gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *, void *); CFATTACH_DECL_NEW(gic_acpi, 0, gic_acpi_match, gic_acpi_attach, NULL, NULL); @@ -85,6 +91,7 @@ gic_acpi_attach(device_t parent, device_ ACPI_MADT_GENERIC_DISTRIBUTOR *gicd = aux; ACPI_MADT_GENERIC_INTERRUPT *gicc = NULL; bus_space_handle_t bsh; + device_t armgic; int error; acpi_madt_walk(gic_acpi_find_gicc, &gicc); @@ -114,9 +121,11 @@ gic_acpi_attach(device_t parent, device_ .mpcaa_off2 = gicc->BaseAddress - addr, }; - config_found(self, &mpcaa, NULL); + armgic = config_found(self, &mpcaa, NULL); arm_fdt_irq_set_handler(armgic_irq_handler); + + acpi_madt_walk(gic_acpi_find_msi_frame, armgic); } static ACPI_STATUS @@ -131,3 +140,44 @@ gic_acpi_find_gicc(ACPI_SUBTABLE_HEADER return AE_LIMIT; } + +static ACPI_STATUS +gic_acpi_find_msi_frame(ACPI_SUBTABLE_HEADER *hdrp, void *aux) +{ + ACPI_MADT_GENERIC_MSI_FRAME *msi_frame = (ACPI_MADT_GENERIC_MSI_FRAME *)hdrp; + struct gic_v2m_frame *frame; + struct pic_softc *pic = pic_list[0]; + device_t armgic = aux; + + if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_MSI_FRAME) + return AE_OK; + + frame = kmem_zalloc(sizeof(*frame), KM_SLEEP); + frame->frame_reg = msi_frame->BaseAddress; + frame->frame_pic = pic; + if (msi_frame->Flags & ACPI_MADT_OVERRIDE_SPI_VALUES) { + frame->frame_base = msi_frame->SpiBase; + frame->frame_count = msi_frame->SpiCount; + } else { + bus_space_tag_t bst = &arm_generic_bs_tag; + bus_space_handle_t bsh; + if (bus_space_map(bst, frame->frame_reg, GICMSIFRAME_SIZE, 0, &bsh) != 0) { + printf("%s: failed to map frame\n", __func__); + return AE_OK; + } + const uint32_t typer = bus_space_read_4(bst, bsh, GIC_MSI_TYPER); + bus_space_unmap(bst, bsh, GICMSIFRAME_SIZE); + + frame->frame_base = __SHIFTOUT(typer, GIC_MSI_TYPER_BASE); + frame->frame_count = __SHIFTOUT(typer, GIC_MSI_TYPER_NUMBER); + } + + if (gic_v2m_init(frame, armgic, msi_frame->MsiFrameId) != 0) + aprint_error_dev(armgic, "failed to initialize GICv2m\n"); + else + aprint_normal_dev(armgic, "GICv2m @ %#" PRIx64 ", SPIs %u-%u\n", + (uint64_t)frame->frame_reg, frame->frame_base, + frame->frame_base + frame->frame_count); + + return AE_OK; +} Index: src/sys/arch/arm/cortex/files.cortex diff -u src/sys/arch/arm/cortex/files.cortex:1.8 src/sys/arch/arm/cortex/files.cortex:1.9 --- src/sys/arch/arm/cortex/files.cortex:1.8 Wed Aug 8 19:02:28 2018 +++ src/sys/arch/arm/cortex/files.cortex Sun Oct 21 00:42:05 2018 @@ -1,4 +1,4 @@ -# $NetBSD: files.cortex,v 1.8 2018/08/08 19:02:28 jmcneill Exp $ +# $NetBSD: files.cortex,v 1.9 2018/10/21 00:42:05 jmcneill Exp $ defflag opt_cpu_in_cksum.h NEON_IN_CKSUM @@ -15,6 +15,7 @@ file arch/arm/cortex/armperiph.c armper device armgic: pic, pic_splfuncs attach armgic at mpcorebus file arch/arm/cortex/gic.c armgic +file arch/arm/cortex/gic_v2m.c armgic & pci & __have_pci_msi_msix # ARM Generic Interrupt Controller v3+ device gicvthree: pic, pic_splfuncs Index: src/sys/arch/arm/fdt/acpi_fdt.c diff -u src/sys/arch/arm/fdt/acpi_fdt.c:1.3 src/sys/arch/arm/fdt/acpi_fdt.c:1.4 --- src/sys/arch/arm/fdt/acpi_fdt.c:1.3 Mon Oct 15 11:35:03 2018 +++ src/sys/arch/arm/fdt/acpi_fdt.c Sun Oct 21 00:42:05 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: acpi_fdt.c,v 1.3 2018/10/15 11:35:03 jmcneill Exp $ */ +/* $NetBSD: acpi_fdt.c,v 1.4 2018/10/21 00:42:05 jmcneill Exp $ */ /*- * Copyright (c) 2015-2017 Jared McNeill <jmcne...@invisible.ca> @@ -27,7 +27,7 @@ */ #include <sys/cdefs.h> -__KERNEL_RCSID(0, "$NetBSD: acpi_fdt.c,v 1.3 2018/10/15 11:35:03 jmcneill Exp $"); +__KERNEL_RCSID(0, "$NetBSD: acpi_fdt.c,v 1.4 2018/10/21 00:42:05 jmcneill Exp $"); #include <sys/param.h> #include <sys/bus.h> @@ -94,6 +94,9 @@ acpi_fdt_attach(device_t parent, device_ /*PCI_FLAGS_IO_OKAY |*/ PCI_FLAGS_MEM_OKAY | PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; +#ifdef __HAVE_PCI_MSI_MSIX + aa.aa_pciflags |= PCI_FLAGS_MSI_OKAY; +#endif aa.aa_ic = 0; aa.aa_dmat = faa->faa_dmat; #ifdef _PCI_HAVE_DMA64 Index: src/sys/arch/arm/include/pci_machdep.h diff -u src/sys/arch/arm/include/pci_machdep.h:1.13 src/sys/arch/arm/include/pci_machdep.h:1.14 --- src/sys/arch/arm/include/pci_machdep.h:1.13 Thu Sep 6 22:30:34 2018 +++ src/sys/arch/arm/include/pci_machdep.h Sun Oct 21 00:42:06 2018 @@ -1,4 +1,4 @@ -/* $NetBSD: pci_machdep.h,v 1.13 2018/09/06 22:30:34 jmcneill Exp $ */ +/* $NetBSD: pci_machdep.h,v 1.14 2018/10/21 00:42:06 jmcneill Exp $ */ /* * Modified for arm32 by Mark Brinicombe @@ -48,7 +48,29 @@ */ typedef struct arm32_pci_chipset *pci_chipset_tag_t; typedef u_long pcitag_t; -typedef u_long pci_intr_handle_t; +typedef uint64_t pci_intr_handle_t; + +/* + * pci_intr_handle_t fields + */ +#define ARM_PCI_INTR_MSI_VEC 0x000007ff00000000ULL +#define ARM_PCI_INTR_MPSAFE 0x0000000080000000ULL +#define ARM_PCI_INTR_MSIX 0x0000000040000000ULL +#define ARM_PCI_INTR_MSI 0x0000000020000000ULL +#define ARM_PCI_INTR_FRAME 0x0000000000ff0000ULL +#define ARM_PCI_INTR_IRQ 0x000000000000ffffULL + +#ifdef __HAVE_PCI_MSI_MSIX +/* + * PCI MSI/MSI-X support + */ +typedef enum { + PCI_INTR_TYPE_INTX = 0, + PCI_INTR_TYPE_MSI, + PCI_INTR_TYPE_MSIX, + PCI_INTR_TYPE_SIZE, +} pci_intr_type_t; +#endif /* __HAVE_PCI_MSI_MSIX */ /* * Forward declarations. @@ -87,6 +109,26 @@ struct arm32_pci_chipset { #endif void (*pc_conf_interrupt)(void *, int, int, int, int, int *); +#ifdef __HAVE_PCI_MSI_MSIX + void *pc_msi_v; + pci_intr_type_t (*pc_intr_type)(void *, pci_intr_handle_t); + int (*pc_intr_alloc)(const struct pci_attach_args *, + pci_intr_handle_t **, int *, pci_intr_type_t); + void (*pc_intr_release)(void *, pci_intr_handle_t *, int); + int (*pc_intx_alloc)(const struct pci_attach_args *, + pci_intr_handle_t **); + int (*pc_msi_alloc)(const struct pci_attach_args *, + pci_intr_handle_t **, int *); + int (*pc_msi_alloc_exact)(const struct pci_attach_args *, + pci_intr_handle_t **, int); + int (*pc_msix_alloc)(const struct pci_attach_args *, + pci_intr_handle_t **, int *); + int (*pc_msix_alloc_exact)(const struct pci_attach_args *, + pci_intr_handle_t **, int); + int (*pc_msix_alloc_map)(const struct pci_attach_args *, + pci_intr_handle_t **, u_int *, int); +#endif + uint32_t pc_cfg_cmd; }; @@ -131,4 +173,22 @@ pci_intr_setattr(pci_chipset_tag_t pc, p return pc->pc_intr_setattr(pc, ihp, attr, data); } +#ifdef __HAVE_PCI_MSI_MSIX +pci_intr_type_t pci_intr_type(pci_chipset_tag_t, pci_intr_handle_t); +int pci_intr_alloc(const struct pci_attach_args *, pci_intr_handle_t **, + int *, pci_intr_type_t); +void pci_intr_release(pci_chipset_tag_t, pci_intr_handle_t *, int); +int pci_intx_alloc(const struct pci_attach_args *, pci_intr_handle_t **); +int pci_msi_alloc(const struct pci_attach_args *, pci_intr_handle_t **, + int *); +int pci_msi_alloc_exact(const struct pci_attach_args *, + pci_intr_handle_t **, int); +int pci_msix_alloc(const struct pci_attach_args *, pci_intr_handle_t **, + int *); +int pci_msix_alloc_exact(const struct pci_attach_args *, + pci_intr_handle_t **, int); +int pci_msix_alloc_map(const struct pci_attach_args *, pci_intr_handle_t **, + u_int *, int); +#endif /* __HAVE_PCI_MSI_MSIX */ + #endif /* _ARM_PCI_MACHDEP_H_ */ Index: src/sys/arch/evbarm/conf/files.evbarm diff -u src/sys/arch/evbarm/conf/files.evbarm:1.31 src/sys/arch/evbarm/conf/files.evbarm:1.32 --- src/sys/arch/evbarm/conf/files.evbarm:1.31 Sat Aug 18 09:29:45 2018 +++ src/sys/arch/evbarm/conf/files.evbarm Sun Oct 21 00:42:06 2018 @@ -1,4 +1,4 @@ -# $NetBSD: files.evbarm,v 1.31 2018/08/18 09:29:45 rin Exp $ +# $NetBSD: files.evbarm,v 1.32 2018/10/21 00:42:06 jmcneill Exp $ # # First try for arm-specific configuration info # @@ -36,6 +36,10 @@ include "dev/sdmmc/files.sdmmc" # SD/M include "dev/scsipi/files.scsipi" # SCSI devices include "dev/usb/files.usb" # USB devices +# +# Machine-dependent drivers +# +include "arch/arm/pci/files.pci" # MD PCI support code # Kernel boot arguments defparam opt_machdep.h BOOT_ARGS Index: src/sys/arch/evbarm/conf/std.generic64 diff -u src/sys/arch/evbarm/conf/std.generic64:1.7 src/sys/arch/evbarm/conf/std.generic64:1.8 --- src/sys/arch/evbarm/conf/std.generic64:1.7 Tue Oct 16 10:25:33 2018 +++ src/sys/arch/evbarm/conf/std.generic64 Sun Oct 21 00:42:06 2018 @@ -1,4 +1,4 @@ -# $NetBSD: std.generic64,v 1.7 2018/10/16 10:25:33 jmcneill Exp $ +# $NetBSD: std.generic64,v 1.8 2018/10/21 00:42:06 jmcneill Exp $ # # generic NetBSD/evbarm64 with FDT support @@ -18,6 +18,7 @@ options FDT # Flattened Device Tree options FPU_VFP options PCI_NETBSD_CONFIGURE options __HAVE_PCI_CONF_HOOK +options __HAVE_PCI_MSI_MSIX # XXXNH not yet #options __HAVE_CPU_UAREA_ALLOC_IDLELWP Added files: Index: src/sys/arch/arm/cortex/gic_v2m.c diff -u /dev/null src/sys/arch/arm/cortex/gic_v2m.c:1.1 --- /dev/null Sun Oct 21 00:42:06 2018 +++ src/sys/arch/arm/cortex/gic_v2m.c Sun Oct 21 00:42:05 2018 @@ -0,0 +1,218 @@ +/* $NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $ */ + +/*- + * Copyright (c) 2018 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jared McNeill <jmcne...@invisible.ca>. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#define _INTR_PRIVATE + +#include <sys/cdefs.h> +__KERNEL_RCSID(0, "$NetBSD: gic_v2m.c,v 1.1 2018/10/21 00:42:05 jmcneill Exp $"); + +#include <sys/param.h> +#include <sys/kmem.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <arm/pic/picvar.h> +#include <arm/cortex/gic_v2m.h> + +static int +gic_v2m_msi_alloc_spi(struct gic_v2m_frame *frame, int count, + const struct pci_attach_args *pa) +{ + int spi, n; + + for (spi = frame->frame_base; + spi < frame->frame_base + frame->frame_count; ) { + if (frame->frame_pa[spi] == NULL) { + for (n = 1; n < count; n++) + if (frame->frame_pa[spi + n] != NULL) + goto next_spi; + + for (n = 0; n < count; n++) + frame->frame_pa[spi + n] = pa; + + return spi; + } +next_spi: + spi += count; + } + + return -1; +} + +static void +gic_v2m_msi_free_spi(struct gic_v2m_frame *frame, int spi) +{ + frame->frame_pa[spi] = NULL; +} + +static int +gic_v2m_msi_available_spi(struct gic_v2m_frame *frame) +{ + int spi, n; + + for (spi = frame->frame_base, n = 0; + spi < frame->frame_base + frame->frame_count; + spi++) { + if (frame->frame_pa[spi] == NULL) + n++; + } + + return n; +} + +static void +gic_v2m_msi_enable(struct gic_v2m_frame *frame, int spi) +{ + const struct pci_attach_args *pa = frame->frame_pa[spi]; + pci_chipset_tag_t pc = pa->pa_pc; + pcitag_t tag = pa->pa_tag; + pcireg_t ctl; + int off; + + if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) + panic("gic_v2m_msi_enable: device is not MSI-capable"); + + const uint64_t addr = frame->frame_reg + GIC_MSI_SETSPI; + ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); + if (ctl & PCI_MSI_CTL_64BIT_ADDR) { + pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_LO, + addr & 0xffffffff); + pci_conf_write(pc, tag, off + PCI_MSI_MADDR64_HI, + (addr >> 32) & 0xffffffff); + pci_conf_write(pc, tag, off + PCI_MSI_MDATA64, spi); + } else { + pci_conf_write(pc, tag, off + PCI_MSI_MADDR, + addr & 0xffffffff); + pci_conf_write(pc, tag, off + PCI_MSI_MDATA, spi); + } + ctl |= PCI_MSI_CTL_MSI_ENABLE; + pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); +} + +static void +gic_v2m_msi_disable(struct gic_v2m_frame *frame, int spi) +{ + const struct pci_attach_args *pa = frame->frame_pa[spi]; + pci_chipset_tag_t pc = pa->pa_pc; + pcitag_t tag = pa->pa_tag; + pcireg_t ctl; + int off; + + if (!pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL)) + panic("gic_v2m_msi_enable: device is not MSI-capable"); + + ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL); + ctl &= ~PCI_MSI_CTL_MSI_ENABLE; + pci_conf_write(pc, tag, off + PCI_MSI_CTL, ctl); +} + +static pci_intr_handle_t * +gic_v2m_msi_alloc(struct arm_pci_msi *msi, int *count, + const struct pci_attach_args *pa, bool exact) +{ + struct gic_v2m_frame * const frame = msi->msi_priv; + pci_intr_handle_t *vectors; + int n; + + const int avail = gic_v2m_msi_available_spi(frame); + if (exact && *count > avail) + return NULL; + + while (*count > avail) { + if (avail < *count) + (*count) >>= 1; + } + if (*count == 0) + return NULL; + + const int spi_base = gic_v2m_msi_alloc_spi(frame, *count, pa); + if (spi_base == -1) + return NULL; + + vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP); + for (n = 0; n < *count; n++) { + const int spi = spi_base + n; + vectors[n] = ARM_PCI_INTR_MSI | + __SHIFTIN(spi, ARM_PCI_INTR_IRQ) | + __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) | + __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME); + + gic_v2m_msi_enable(frame, spi); + } + + return vectors; +} + +static void * +gic_v2m_msi_intr_establish(struct arm_pci_msi *msi, + pci_intr_handle_t ih, int ipl, int (*func)(void *), void *arg) +{ + struct gic_v2m_frame * const frame = msi->msi_priv; + + const int spi = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); + const int mpsafe = (ih & ARM_PCI_INTR_MPSAFE) ? IST_MPSAFE : 0; + + return pic_establish_intr(frame->frame_pic, spi, ipl, + IST_EDGE | mpsafe, func, arg); +} + +static void +gic_v2m_msi_intr_release(struct arm_pci_msi *msi, pci_intr_handle_t *pih, + int count) +{ + struct gic_v2m_frame * const frame = msi->msi_priv; + int n; + + for (n = 0; n < count; n++) { + const int spi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ); + gic_v2m_msi_disable(frame, spi); + gic_v2m_msi_free_spi(frame, spi); + struct intrsource * const is = + frame->frame_pic->pic_sources[spi]; + if (is != NULL) + pic_disestablish_source(is); + } +} + +int +gic_v2m_init(struct gic_v2m_frame *frame, device_t dev, uint32_t frame_id) +{ + struct arm_pci_msi *msi = &frame->frame_msi; + + msi->msi_dev = dev; + msi->msi_priv = frame; + msi->msi_alloc = gic_v2m_msi_alloc; + msi->msi_intr_establish = gic_v2m_msi_intr_establish; + msi->msi_intr_release = gic_v2m_msi_intr_release; + + return arm_pci_msi_add(msi); +} Index: src/sys/arch/arm/cortex/gic_v2m.h diff -u /dev/null src/sys/arch/arm/cortex/gic_v2m.h:1.1 --- /dev/null Sun Oct 21 00:42:06 2018 +++ src/sys/arch/arm/cortex/gic_v2m.h Sun Oct 21 00:42:05 2018 @@ -0,0 +1,51 @@ +/* $NetBSD: gic_v2m.h,v 1.1 2018/10/21 00:42:05 jmcneill Exp $ */ + +/*- + * Copyright (c) 2018 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jared McNeill <jmcne...@invisible.ca>. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_CORTEX_GIC_V2M_H +#define _ARM_CORTEX_GIC_V2M_H + +#include <arm/pci/pci_msi_machdep.h> +#include <arm/cortex/gic_reg.h> + +struct gic_v2m_frame { + uint64_t frame_reg; + struct pic_softc *frame_pic; + uint16_t frame_base; + uint16_t frame_count; + + const struct pci_attach_args *frame_pa[GICC_IAR_IRQ]; + + struct arm_pci_msi frame_msi; +}; + +int gic_v2m_init(struct gic_v2m_frame *, device_t, uint32_t); + +#endif /* !_ARM_CORTEX_GIC_V2M_H */ Index: src/sys/arch/arm/pci/files.pci diff -u /dev/null src/sys/arch/arm/pci/files.pci:1.1 --- /dev/null Sun Oct 21 00:42:06 2018 +++ src/sys/arch/arm/pci/files.pci Sun Oct 21 00:42:06 2018 @@ -0,0 +1,4 @@ +# $NetBSD: files.pci,v 1.1 2018/10/21 00:42:06 jmcneill Exp $ + +# PCI MSI/MSI-X support +file arch/arm/pci/pci_msi_machdep.c pci & __have_pci_msi_msix Index: src/sys/arch/arm/pci/pci_msi_machdep.c diff -u /dev/null src/sys/arch/arm/pci/pci_msi_machdep.c:1.1 --- /dev/null Sun Oct 21 00:42:06 2018 +++ src/sys/arch/arm/pci/pci_msi_machdep.c Sun Oct 21 00:42:06 2018 @@ -0,0 +1,241 @@ +/* $NetBSD: pci_msi_machdep.c,v 1.1 2018/10/21 00:42:06 jmcneill Exp $ */ + +/*- + * Copyright (c) 2018 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jared McNeill <jmcne...@invisible.ca>. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__KERNEL_RCSID(0, "$NetBSD: pci_msi_machdep.c,v 1.1 2018/10/21 00:42:06 jmcneill Exp $"); + +#include <sys/kernel.h> +#include <sys/kmem.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <arm/pic/picvar.h> + +#include <arm/pci/pci_msi_machdep.h> + +static SIMPLEQ_HEAD(, arm_pci_msi) arm_pci_msi_list = + SIMPLEQ_HEAD_INITIALIZER(arm_pci_msi_list); + +static struct arm_pci_msi * +arm_pci_msi_find_frame(pci_intr_handle_t ih) +{ + struct arm_pci_msi *msip; + + const int id = __SHIFTOUT(ih, ARM_PCI_INTR_FRAME); + + SIMPLEQ_FOREACH(msip, &arm_pci_msi_list, msi_link) + if (id == msip->msi_id) + return msip; + + return NULL; +} + +static int +arm_pci_msi_alloc_common(pci_intr_handle_t **ihps, int *count, const struct pci_attach_args *pa, bool exact) +{ + pci_intr_handle_t *vectors; + struct arm_pci_msi *msi; + + if ((pa->pa_flags & PCI_FLAGS_MSI_OKAY) == 0) + return ENODEV; + + msi = SIMPLEQ_FIRST(&arm_pci_msi_list); /* XXX multiple frame support */ + if (msi == NULL || msi->msi_alloc == NULL) + return EINVAL; + + vectors = msi->msi_alloc(msi, count, pa, exact); + if (vectors == NULL) + return ENOMEM; + + *ihps = vectors; + + return 0; +} + +/* + * arm_pci_msi MD API + */ + +int +arm_pci_msi_add(struct arm_pci_msi *msi) +{ + SIMPLEQ_INSERT_TAIL(&arm_pci_msi_list, msi, msi_link); + + return 0; +} + +void * +arm_pci_msi_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih, + int ipl, int (*func)(void *), void *arg) +{ + struct arm_pci_msi *msi; + + msi = arm_pci_msi_find_frame(pih); + if (msi == NULL) + return NULL; + + return msi->msi_intr_establish(msi, pih, ipl, func, arg); +} + +/* + * pci_msi(9) implementation + */ + +int +pci_msi_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, int *count) +{ + return arm_pci_msi_alloc_common(ihps, count, pa, false); +} + +int +pci_msi_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, int count) +{ + return arm_pci_msi_alloc_common(ihps, &count, pa, true); +} + +int +pci_msix_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, int *count) +{ + return EOPNOTSUPP; +} + +int +pci_msix_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, int count) +{ + return EOPNOTSUPP; +} + +int +pci_msix_alloc_map(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, u_int *table_indexes, int count) +{ + return EOPNOTSUPP; +} + +int +pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihp) +{ + pci_intr_handle_t *pih; + + if (ihp == NULL) + return EINVAL; + + pih = kmem_alloc(sizeof(*pih), KM_SLEEP); + if (pci_intr_map(pa, pih) != 0) { + kmem_free(pih, sizeof(*pih)); + return EINVAL; + } + *ihp = pih; + + return 0; +} + +int +pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, int *counts, pci_intr_type_t max_type) +{ + int intx_count, msi_count, msix_count, error; + + error = EINVAL; + intx_count = 1; + msi_count = 1; + msix_count = 0; + + if (counts != NULL) { + switch (max_type) { + case PCI_INTR_TYPE_MSIX: + msix_count = counts[PCI_INTR_TYPE_MSIX]; + /* FALLTHROUGH */ + case PCI_INTR_TYPE_MSI: + msi_count = counts[PCI_INTR_TYPE_MSI]; + /* FALLTHROUGH */ + case PCI_INTR_TYPE_INTX: + intx_count = counts[PCI_INTR_TYPE_INTX]; + if (intx_count > 1) + return EINVAL; + break; + default: + return EINVAL; + } + memset(counts, 0, sizeof(*counts) * PCI_INTR_TYPE_SIZE); + } + + if (msix_count == -1) + msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag); + if (msix_count > 0 && (error = pci_msix_alloc_exact(pa, ihps, msix_count)) == 0) { + if (counts == NULL) + return EINVAL; + counts[PCI_INTR_TYPE_MSIX] = msix_count; + return 0; + } + + if (msi_count == -1) + msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag); + if (msi_count > 0 && (error = pci_msi_alloc_exact(pa, ihps, msi_count)) == 0) { + if (counts != NULL) + counts[PCI_INTR_TYPE_MSI] = msi_count; + return 0; + } + + if (intx_count > 0 && (error = pci_intx_alloc(pa, ihps)) == 0) { + if (counts != NULL) + counts[PCI_INTR_TYPE_INTX] = intx_count; + return 0; + } + + return error; +} + +void +pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count) +{ + struct arm_pci_msi *msi; + + if (pih == NULL || count == 0) + return; + + msi = arm_pci_msi_find_frame(pih[0]); + KASSERT(msi != NULL); + msi->msi_intr_release(msi, pih, count); + + kmem_free(pih, sizeof(*pih) * count); +} + +pci_intr_type_t +pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih) +{ + if (ih & ARM_PCI_INTR_MSIX) + return PCI_INTR_TYPE_MSIX; + + if (ih & ARM_PCI_INTR_MSI) + return PCI_INTR_TYPE_MSI; + + return PCI_INTR_TYPE_INTX; +} Index: src/sys/arch/arm/pci/pci_msi_machdep.h diff -u /dev/null src/sys/arch/arm/pci/pci_msi_machdep.h:1.1 --- /dev/null Sun Oct 21 00:42:06 2018 +++ src/sys/arch/arm/pci/pci_msi_machdep.h Sun Oct 21 00:42:06 2018 @@ -0,0 +1,57 @@ +/* $NetBSD: pci_msi_machdep.h,v 1.1 2018/10/21 00:42:06 jmcneill Exp $ */ + +/*- + * Copyright (c) 2018 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jared McNeill <jmcne...@invisible.ca>. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _ARM_PCI_MSI_MACHDEP_H +#define _ARM_PCI_MSI_MACHDEP_H + +#include <sys/queue.h> +#include <arm/pic/picvar.h> + +struct arm_pci_msi { + device_t msi_dev; + uint8_t msi_id; /* software ID */ + + void * msi_priv; + + pci_intr_handle_t * (*msi_alloc)(struct arm_pci_msi *, int *, const struct pci_attach_args *, bool); + void * (*msi_intr_establish)(struct arm_pci_msi *, + pci_intr_handle_t, int, int (*)(void *), void *); + void (*msi_intr_release)(struct arm_pci_msi *, + pci_intr_handle_t *, int); + + SIMPLEQ_ENTRY(arm_pci_msi) msi_link; +}; + +int arm_pci_msi_add(struct arm_pci_msi *); +void * arm_pci_msi_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, + int, int (*)(void *), void *); + +#endif /* !_ARM_PCI_MSI_MACHDEP_H */